STM32 - memory, I2C protocol

Common memory classification

Memory can be divided into volatile memory and nonvolatile memory , among Volatile memory yes RAM,RAM Include DRAM（SDRAM,DDR SDRAM,DDRII SDRAM,DDRIII SDRAM） and SRAM, Nonvolatile memory , Include ROM（MASK ROM,PROM【OPTROM,EPROM,EEPROM】,FLASH【NOR FLASH,NAND FLASH】, Compact disc , floppy disk , Mechanical drive ）

RAM:

(1) SRAM- Static random access memory

Store data in a latch

(2) DRAM- Dynamic RAM

Data is represented by capacitance

Random access refers to when messages in memory are read or written , The time required is independent of the location of this information

characteristic	DRAM	SRAM
Access speed	slower	Faster
Integration	Higher	The lower
Production costs	The lower	Higher
Do you need to refresh	yes	no

ROM—— read-only memory

MASK ROM： The internal data content is solidified when leaving the factory , Do not modify the

OPT ROM： The user can write the internal data content once , It cannot be modified later

EP ROM： Rewritable , But it needs to be wiped with special UV irradiation equipment

EEP ROM： Rewritable , Electric erasure , Easy to use

FLASH—— Flash memory

Nor Flash—— Internal storage block or non mode connection

Nand Flash—— The internal storage block is connected in a non-linear way

characteristic	NOR FLASH	NAND FLASH
Storage cost of the same capacity	More expensive	It's cheaper
Integration	The lower	Higher
Media type	random packing	Continuous storage
Address line and data line	Separate... Independently	share
Erase unit	In sectors / Block erase	In sectors / Block erase
Read and write unit	Can read and write based on bytes	Must read and write in blocks
Read speed	Higher	The lower
Write Entry speed	The lower	Higher
Bad block	Less	More
Do you support XIP	Support	I won't support it

I2C—— Reading and writing EEPROM

I2C Introduction to communication protocol

I2C The communication protocol is composed of Phiilps company-developed , Because it is less , The hardware implementation is simple , Strong expandability , Unwanted USART,CAN And so on , Now it is widely used in many integrated circuits in the system (IC) Communication between

I2C Physical layer characteristics

（1） It's a Support multi device bus , Bus refers to the signal line shared by multiple devices , In a I2C In the communication bus . Can connect multiple IC Communication equipment , Support multiple communication hosts and multiple communication slaves

（2） One I2C The bus only uses two bus lines , A two-way serial data line (SDA), A serial clock line (SCL), Data lines and used to represent data , The clock line is used for data synchronization

（3） Each device connected to the bus has a separate address , The host can use this address to access different devices

（4） The bus is connected to the power supply through pull-up resistor , When I2C When the device is idle , It will output a high resistance state , When all devices are idle , When both output high resistance states , Pull the bus to high level by pull-up resistor

（5） When multiple hosts use the bus at the same time , To prevent data conflicts , Arbitration will be used to determine which device occupies the bus

Arbitration method ：I2C Generally, open drain structure is used , Line and logic can be realized , As long as there is a device output low level on the bus , The level of this bus will become low , Even if other devices output high level , The whole bus is always kept low . When multiple hosts transmit data , such as A,B All hosts need to transmit data on this bus , hypothesis A Transmit a high level ,B Transmit a low level , Because of line and logic ,SDA The bus is low , At this time, the device will compare the transmitted data with the status of the bus , because A Is a high level , Inconsistent with the bus state ,A You lose the right to use the bus ,B Is a low level , Consistent with the bus state ,B Obtain the right to use .

（5） There are three transmission modes , The standard mode transmission rate is 100kbit/s, The fast mode is 400kbit/s, In high-speed mode 3.4Mbit/s, But at present, most of them I2C The device does not support high speed mode

（6） Connected to the same bus IC The quantity is affected by the maximum capacitance of the bus 400pF Limit

I2C Protocol layer features

I2C The protocol defines the start and notification signals of communication , Data validity , Respond to , arbitration , Clock synchronization and address broadcast

Write process analysis ： S Is the transmission start signal , Then comes the slave address , That is, the target of transmission , Then there is a read-write signal bit , Specify the destination of the signal , If R/W by 0, Indicates that the host wants to perform write operations on the slave , When the slave receives the data , Will send a response signal to the host ( The reply ACK), Indicates that the signal has been received , When the host receives this signal , Will start sending data , If the host does not wait for the reply signal , It means that the device is not on this bus , At this time, the master and slave occupy the bus for data interaction , At the end of the agreement is P, Stop bit .

  Read process analysis ： S Is the transmission start signal （ Host send ）, Then comes the slave address , That is, the target of reading , Then there is a read-write signal bit , Specify the destination of the signal , If R/W by 1, Indicates that the host wants to perform read operations on the slave , When the slave receives the signal from the host （ read ） after , Will send a response signal to the host ( The reply ACK), Indicates that the signal has been received , And will DATA Transmitted from slave to host , After data transmission , The master sends a reply flag to the slave , Indicates that data has been received , The slave will continue to transmit data to the host , Until the host does not answer （NACK）, The slave stops data transmission , At the end of the agreement is P, Stop bit .

  Start and stop signals of communication

 （1） When SCL For high voltage ,SDA Switching from high level to low level , This situation indicates the beginning of communication

（2） When SCL Low power level ,SDA Switch from low level to high level , This situation means that communication stops

（3） Start and stop signals are usually generated by the host computer

Data validity

I2C Use SDA Signal lines to transmit data , Use SCL Signal line for data synchronization ,SDA The data line is in SCL One bit of data per clock cycle

SCL When it's high level SDA Indicates that the data is valid , That at this time SDA Indicates data for high level 1, Show data for low level 0, When SCL Low power level ,SDA Invalid data , Usually this time SDA Carry out level switching , Prepare for the next presentation of data

Address and data direction

I2C Each device on the bus has its own independent address , When the host initiates communication , adopt SDA Signal line sending device address (SLAVE_ADDRESS) To find the slave , The device address can be 7 Bits or 10 position

Immediately following the device address is the data bit R/W Used to indicate the direction of data transmission , The data direction bit is 1 Indicates that the master reads data from the slave , by 0 Indicates that the host writes data to the slave

Respond to

I2C The data transmission of each address has corresponding , Include accordingly “ The reply （ACK）” And non response (NACK)

  The host generates a clock during transmission , On the ninth clock , The data sender will release SDA Control right , Controlled by the data receiver SDA, if SDA High level , Indicates a non response signal , A low level indicates a reply signal