FPGA based: moving target detection (supplementary simulation results, available)

One 、 Connected to a

      See this article directly for development and design ： be based on FPGA： Moving target detection （ Schematic diagram + Source code + Hardware options , Available design ） Here is the simulation result , Many friends reacted , It's not easy to do the paper without simulation results .
      The complete source code project is downloaded here ： be based on FPGA Moving target detection （ Hardware + Schematic diagram + Source code + Simulation + Design document ） Again , I can pay half price for private messages , Because you can get rid of the platform fees .

Two 、 To enter the body （ Frame difference method Modelsim Simulation ）

      Build a video stream Modelsim Simulation , Need to simulate a video sequence , Used to verify the algorithm , And make effective use of Matlab Tools put static pictures “ Break up ” Save to txt In the text , for Modesim Read , And then through Matalb“ Reappear ” Processed text .

     Test0.bmp The test image ,matlab Produced rgb txt Data text ,
     image_r_data.txt image_g_data.txt image_b_data.txt

     Test1.bmp The test image
     image_r_data_o.txt image_g_data_o.txt image_b_data_o.txt

     Verilog Realize the investigation law , after modelsim The simulation results show that , function smy_image_show.m
     data_r_out.txt data_g_out.txt data_b_out.txt

Rgb2yuv Simulation waveform , Don't talk much , Look at the formula

Diff_frame Module simulation waveform ：data_next - data_cur The results obtained are as follows post_img_Bit When 8’d130-8’D16
Greater than Set threshold 15 The target area , Set to 255

Corrosion and expansion simulation waveform , The following is *p11,p12 9 Pixel data is 3x3 Image template , Through row cache design （ Cached 2 Row image data ）, The second after the yellow line 3 That's ok , Get complete 3x3 Image template

Find_box Module simulation waveform , Gray frame difference method to get binary image , Then design the bounding box to get up, down, left and right 4 Point pixel coordinates , Frame the target area .

Data acquisition module ：

In order to visually see the line field signal , Simulate camera timing , One frame of data is reduced to 4 Row data , As shown in the figure below :

As shown in the figure below , Achieve output RGB565 When the format , Two pixel clocks in succession 8bit The splicing of data into 16bit The data of

I2C Control timing module ：

                                                                                 I2C Timing simulation diagram

The use of I2C The system clock is 100MHz, By dividing the frequency of the system clock, we can get i2c_sclk The clock is 100KHz, But it cannot be directly used Verilog Designed drive clock , So here we use enable clock to realize .i2c_capture_en Sample at the middle point of high level ,i2c_transfer_en Transmit data at the low-level intermediate point ,I2C The configured data is written in the first byte 8’H42 Camera for writing timing ID Address , The register address data will be written in the second byte , Then the register data is written in the third byte . Due to the response bit ACK The existence of , It takes 9 Clock cycles .

Two 、VGA modular ：

chart 2.17 I2C Timing simulation diagram
Pictured 2.17 Shown ,I2C sequential Modelsim Simulation results . This article is designed to use I2C The system clock is 100MHz, By dividing the frequency of the system clock, we can get i2c_sclk The clock is 100KHz, But it cannot be directly used Verilog Designed drive clock , So here we use enable clock to realize .i2c_capture_en Sample at the middle point of high level ,i2c_transfer_en Transmit data at the low-level intermediate point ,I2C The configured data is written in the first byte 8’H42 Camera for writing timing ID Address , The register address data will be written in the second byte , Then the register data is written in the third byte . Due to the response bit ACK The existence of , It takes 9 Clock cycles .

notes ： You can confide in me if you need a watermark free picture .