Hongmeng porting i.mx6ull (VIII) memory mapping (based on imx6ull)

1.ARM Introduction to architecture memory mapping

Reference material ：DEN0013D_cortex_a_series_PG.pdf.

1.1.1 Page table item

ARM The schema supports first level page table mapping , in other words MMU according to CPU The virtual address sent can be found at No 1 Page tables , From 1 You can know the physical address corresponding to this virtual address in a page table . The smallest unit of address mapping in the first level page table is 1M.

ARM The architecture also supports secondary page table mapping , in other words MMU according to CPU Find the virtual address first 1 Page tables , From 1 You can know page... From a page list 2 Where is the level page table ; Then take out the second 2 Class page table , From 2 The physical address corresponding to this virtual address can only be determined in a page table . The minimum unit of the address mapping of the secondary page table is 4K、1K,Linux Use 4K.

The contents of the first level page table items , Determines that it points to a piece of physical memory , Or do you mean to ask the secondary page table , Here's the picture ：

Page table entry is a 32 A data , There is a physical address stored inside , There is also some control information .
Page entry bit1、bit0 Indicates that it is a first level page entry , It is also a secondary page entry .
For first level page table entries , It contains 1M The physical base address of the space , This is also called segment mapping , This physical address is also known as Section base address .

[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-3bx9JRYm-1654656782577)(pic/06_ Memory mapping /01_pate_table_item.png)]

In the picture above TEX、C、B Can be used to control the access method of this space ： Whether to use Cache、Buffer wait for .
The figure below is too complex , We just need to know ：

• Cannot use... When accessing peripherals Cache、Buffer
• Use... When accessing memory Cache、Buffer It can speed up
• If memory is used as DMA transmission , Do not use Cache、Buffer

As shown in the figure below ：
[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-dNSgoyBj-1654656782577)(pic/06_ Memory mapping /04_memory_type.png)]

1.1.2 First level page table mapping process

When using the first level page table , First set each page table item in memory , Then tell... The base address of the page table MMU, You can start it MMU 了 .

The following figure introduces the address mapping process as an example ：

• ① CPU Send virtual address vaddr, Assuming that 0x12345678

• ② MMU according to vaddr[31:20] Find the first level page table entry

  • Virtual address 0x12345678 It's the... In the virtual address space 0x123 individual 1M
  • So find page... In the table 0x123 term , According to the content of this item, it is a segment page table item
  • The intra segment offset is 0x45678.

• ③ Take the physical base address from this table entry ：Section Base Address, The assumption is 0x81000000

• ④ The physical base address is added with the intra segment offset to obtain ：0x81045678

therefore CPU To access a virtual address 0x12345678 when , In fact, I visited 0x81045678 The physical address of .

[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-eR6NXMxz-1654656782578)(pic/06_ Memory mapping /03_map_example.png)]

1.1.3 Secondary page table mapping process

First set up the first level page table 、 Second level page table , And tell... The first address of the first level page table MMU.

The following figure introduces the address mapping process as an example ：
[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-NrU5GaaZ-1654656782578)(pic/06_ Memory mapping /06_map2_example.png)]

• ① CPU Send virtual address vaddr, Assuming that 0x12345678

• ② MMU according to vaddr[31:20] Find the first level page table entry

  • Virtual address 0x12345678 It's the... In the virtual address space 0x123 individual 1M, So find page... In the table 0x123 term .
  • According to the content of this item, it is a secondary page table item .

• ③ Take the address from this entry , The assumption is address, This represents the physical address of the secondary page table entry ;

• ④ vaddr[19:12] Represents the index in the secondary page table entry index namely 0x45, Find the... In the table entry of the second level page 0x45 term ;

• ⑤ The table item format of the secondary page is as follows
  [ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-wXICSvd4-1654656782578)(pic/06_ Memory mapping /05_second_pate_table_item.png)]

• It contains this 4K or 1K Base address of physical space page base addr, The assumption is 0x81889000

  • It goes with vaddr[11:0] Combine to get the physical address ：0x81889000 + 0x678 = 0x81889678

• therefore CPU To access a virtual address 0x12345678 when , In fact, I visited 0x81889678 The physical address of

1.1.4 cache and buffer

This section refers to ：ARM Of cache And write buffer （write buffer）

Use MMU when , Need to have cache、buffer Knowledge .
The picture below is CPU And memory , Yes cache、buffer( Write buffer ).
Cache It's a high-speed memory ; The write buffer is equivalent to a FIFO, Multiple write operations can be combined and written to memory at one time .
[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-ChjUz2I5-1654656782579)(pic/06_ Memory mapping /07_cpu_cache_buffer.png)]

There is a problem when the program is running “ Locality principle ”, This is divided into time locality 、 Spatial locality .

• Temporal locality ：
  Access to a specific location of memory at a certain point in time , Probably in a short period of time , Will repeatedly visit this location .

• Spatial locality
  Access to a specific location in memory , It is likely to visit its nearby location in the near future .

and CPU Very fast , The speed of memory is relatively slow .
CPU To read and write slow memory , How can we speed up ？
according to “ Locality principle ”, Can be introduced cache：

• Read memory addr Data at

  • Have a look first cache Is there a addr The data of , If there is, directly from cache Return data in ： This is known as cache hit .
  • If cache There is no addr The data of , Then read the data from memory into
    Be careful ： It doesn't just read in a single piece of data , Instead, read in a row of data (cache line).
  • and CPU This is likely to be used again addr The data of , Or use the data near it , Then you can quickly start from cache Data from .

• Writing data

  • CPU When writing data , You can write directly to memory , It's slow ; You can also write the data to cache, It's fast .
  • however cache The data in the must be written into memory after all , There are 2 A writing strategy ：
    • a. Write through (write through)：
      Data should be written at the same time cache And memory , therefore cache Consistent with the data in memory , But it's inefficient .
      Can you improve ？ Sure ！
      Use “ Write buffer ”：cache eldest brother , Just give me the data , Let me write slowly , I promise to help you finish .
      Some write buffers have “ Write merge ” The function of , such as CPU Yes 4 Write instructions ： Write the first 0、1、2、3 Bytes , Every time 1 byte ; The write buffer will put this 4 Merge write operations into one write operation ： Write word.
      For memory , It makes no difference , But for hardware registers , This can lead to problems .
      So for register operations , Will not start buffer function ; For memory operations , such as LCD Explicit memory of , Enable buffer function .
    • b. Write back to (write back)：
      New data is just written cache, Memory will not be written immediately ,cache Inconsistent with the data in memory .
      New data write cache when , This business cache Marked as “ dirty ”(dirty); When cache Not enough time , You need to write dirty data into memory .
      Use the writeback function , Can greatly improve efficiency . But be careful cache And the data in memory are likely to be inconsistent . This needs to be handled carefully in a lot of time ： such as CPU New data has been generated ,DMA Move data from memory to network card , At this time CPU Execute the command to remove the new data from cache Brush to memory . The reverse is the same ,DMA The new data obtained from the network card is stored in the memory ,CPU Put... Before reading data cache Data in is discarded .

Whether to use cache、 Whether to use buffer, There is 4 Combinations of (Linux Kernel files arch\arm\include\asm\pgtable-2level.h)：
[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-TzjmmlqS-1654656782579)(pic/06_ Memory mapping /08_4type_for_cache_buffer.png)]

above 4 The combinations correspond to the items in the table below , One-to-one correspondence ( The following table is from s3c2410 Chip manual , Elevated structure cache、buffer More complicated , But the basics haven't changed )：

Is it enabled? cache	Is it enabled? buffer	explain
0	0	Non-cached, non-buffered (NCNB) read 、 Write directly to the peripheral hardware
0	1	Non-cached buffered (NCB) read 、 Write directly to the peripheral hardware ; Write through buffer Realization ,CPU Do not wait for the write operation to complete ,CPU Will immediately execute the next instruction
1	0	Cached, write-through mode (WT), Write through read ：cache hit From the cahce Reading data ;cache miss A row of data has been entered to cache; Write ： adopt buffer Realization ,CPU Do not wait for the write operation to complete ,CPU Will immediately execute the next instruction
1	1	Cached, write-back mode (WB), Write back to read ：cache hit From the cahce Reading data ;cache miss A row of data has been entered to cache; Write ： adopt buffer Realization ,cache hit New data will not reach the hardware , But in cahce Marked as “ dirty ”;cache miss when , adopt buffer Write hardware ,CPU Do not wait for the write operation to complete ,CPU Will immediately execute the next instruction

The first 1 One is not to use cache Not used buffer, Read and write directly to the hardware , This is suitable for reading and writing registers .

The first 2 One is not to use cache But use buffer, When writing data, you will use buffer To optimize , There may be a “ Write merge ”, This is suitable for the operation of video memory . Because there are few read operations on video memory , It's basically a write operation , The write operation is even if “ Merge ” It doesn't matter .

The first 3 One is to use cache Don't use buffer, Namely “write through”, For read-only devices ： Use... When reading data cache Speed up , There is basically no need to write .

The first 4 One is to use both cache Use again buffer, Suitable for general memory reading and writing .

2. Memory mapped code analysis

Analyze startup file kernel\liteos_a\arch\arm\arm\src\startup\reset_vector_up.S,
The address mapping relationship shown in the following figure can be obtained ：

• Memory address
  • KERNEL_VMM_BASE The starting virtual address , Use Cache, Fast
  • UNCACHED_VMM_BASE The starting virtual address , Don't use Cache, fit DAM transmission 、LCD Framebuffer etc.
• Equipment space ： All kinds of peripherals , such as UART、LCD controller 、I2C controller 、 Interrupt controller
  • PERIPH_DEVICE_BASE The starting virtual address , Don't use Cache Don't use Buffer
  • PERIPH_CACHED_BASE The starting virtual address , Use Cache Use Buffer
  • PERIPH_UNCACHE_BASE The starting virtual address , Don't use Cache But use Buffer

[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-NCVT0Vef-1654656788747)(pic/06_ Memory mapping /01_default_mem_map.png)]

Liteos-a How is the address space allocated ？
KERNEL_VMM_BASE be equal to 0x40000000, And in kernel\liteos_a\kernel\base\include\los_vm_zone.h See the following statement ：

#if (PERIPH_UNCACHED_BASE >= (0xFFFFFFFFU - PERIPH_UNCACHED_SIZE))
#error "Kernel virtual memory space has overflowed!"
#endif

So we can think roughly of ：

• Kernel space ：0x40000000 ~ 0xFFFFFFFF
• User space ：0 ~ 0x3FFFFFFF

3. Memory mapping programming _IMX6ULL

1.1 final result

The modifications made in this chapter will be made as patch files ：

• 02_openharmony_memmap_imx6ull.patch

Patch first ：openharmony_100ask_v1.2.patch,
Patch again ：01_openharmony_add_demo_board.patch
Finally, patch ：02_openharmony_memmap_imx6ull.patch

Be careful ： You may also see patch files for other boards , such as 02_openharmony_memmap_stm32mp157.patch, You can't play at the same time , Because it's all using vendor/democom/demochip Source code in , Only one chip can be supported at the same time

Suppose the catalog openharmony Is unmodified code , Never patched ;
Suppose that the patch file is placed in openharmony The same level directory ;
The patching method is as follows ：

$ cd openharmony
$ patch -p1 < ../openharmony_100ask_v1.2.patch
$ patch -p1 < ../01_openharmony_add_demo_board.patch
$ patch -p1 < ../02_openharmony_memmap_imx6ull.patch 

After patching , You can compile like this ：

$ cd kernel/liteos_a
$ cp tools/build/config/debug/demochip_clang.config .config
$ make clean
$ make

1.2 Field programming

Reference material ：IMX6ULLRM.pdf

1.2.1 Memory address range

[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-bLZbyfRq-1654656798659)(pic/06_ Memory mapping /09_imx6ull_mem_ddr_map.png)]

100ASK_IMX6ULL Development board DDR Capacity is 512M, therefore ：

// vendor\democop\demochip\board\include\board.h
#define DDR_MEM_ADDR 0x80000000
#define DDR_MEM_SIZE 0x20000000

1.2.2 Device address range

IMX6ULL The device address on the chip is too fragmented , from 0 To 0x6FFFFFFF There are involved , There are many reserved addresses in the middle , Enter below ：

[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-Cgi6Jqcq-1654656798660)(pic/06_ Memory mapping /10_imx6ull_device_map.png)] If you put 0 To 0x6FFFFFFF All mapped , Not enough address space ;
The right way Should be to ignore those reserved address spaces , For each module Individually mapped addresses .
however Liteos-a Such code has not yet been implemented ( It is also possible to realize it by yourself , But let's port the smallest system first ).
We must at least map 2 Addresses of devices ：UART1(100ASK_IMX6ULL Development board use UART1)、GIC, Here's the picture ：
[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-FZea9387-1654656798661)(pic/06_ Memory mapping /11_imx6ull_gic_map.png)]

[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-WvGmYq3I-1654656798662)(pic/06_ Memory mapping /12_imx6ull_uart1_map.png)]

therefore ：

// source\vendor\democom\demochip\board\include\board.h
#define PERIPH_PMM_BASE 0x00a00000 // GIC The base address 
#define PERIPH_PMM_SIZE 0x02300000 //  As big as possible , When you use other peripherals in the future, you don't need mapping 

PERIPH_PMM_SIZE It can't be too big , The constraint is ：

#if (PERIPH_UNCACHED_BASE >= (0xFFFFFFFFU - PERIPH_UNCACHED_SIZE))
#error "Kernel virtual memory space has overflowed!"
#endif