Principles of microcomputer Chapter 6 notes arrangement

Command system

Machine instruction set

Command word

A string of bits representing a particular instruction

contain

• opcode
• Operands （ There may be more than one ）
• Operand address

Need to point out that

• Operation type
• Operand type
• Addressing mode

T32

And then there is 16 Bit instructions have 32 Bit instruction , Half word alignment ,32 Bit instruction two and a half words ,16 One place , Pass the half word maximum 5 Bit discrimination

Assembly syntax

$$<opcode>[cond][q][S]<Rd><Rn>[,Oprand2]$$

among <> Mandatory [] Optional

• opcode： Mnemonic , Describe the type of operation
• cond： Condition code
• q： Width selection
  • N-16
  • W-32
• S： Automatically update after adding APSR Flag bit value
• Rd, Target operands , register
• Rn, First source operand , register
• Oprand2： Second source operand , Register or immediate

Condition execution

APSR

• N negative
• Z zero
• C carry
• V overflow
• Q saturated
• GE be used for DSP Expand

Condition code

• EQ be equal to
• NE It's not equal to
• CS carry
• CC Carry to zero
• MI negative
• PL Integer or zero
• VS overflow
• VC No overflow
• HI No sign greater than
• LS Unsigned less than or equal to
• GE Signed greater than or equal to
• LT Signed less than
• LT Signed less than
• GT There is a sign greater than
• LE Unsigned less than or equal to
• AL Unconditional

Mnemonic symbol

• ADD
• LDM Store multiple... Into multiple registers 32 Bit value
• LDR take 32 The bit value is stored in the register
• MOV
• STM Store multiple register values into memory
• STR The of a register 32 The number of bits is stored in memory
• SUB

IT Instructions

Yes

• IT
• ITT
• ITE
• ITTE
• ITTEE

Addressing mode

• Operand addressing

  Data addressing

  Used to determine the address of the operand in the current instruction

• Command addressing

  Determine the next instruction address

Can be divided into

Operand position	Addressing mode
In the instruction	Count now
register	register
	Register displacement
Memory data area	Register indirect
	Register Offset
	Front index
	Post indexing
	Multiple registers
	Stack
Memory code area	PC Relative addressing

• Immediate addressing

  The operand is contained in the instruction , Fetching an instruction fetches the operand

• Register addressing

  Register direct addressing , Make the value in the register an operand

• Register indirection

  The register value is the operand address , The operand itself is in memory

• Register shift addressing

  ARM specific , The register is addressed to the operand and shifted to the real operand

• Register offset addressing

  The operand address is obtained by adding the value stored in the register and the address offset given by the instruction

  This register is the base register , The given offset has

  • Count now
  • register
  • Register shift

• Pre indexed addressing

  Automatically add the base address and offset to form the operand address and write it back to the register , Occurs before addressing , So it is called pre indexing

  It is good for looping statements

• Post indexing

  Occurs after addressing

• Multi register addressing

  Some instructions can load contiguous storage areas into multiple registers

  • LDM{addr_mode}{!},

  Rn Is the base register ,{！} Indicates that the modified address needs to be written back to the base address register ,{addr_mode} Optional I（ Increasing ）/D（ Decline ） and A（ After taking the value ）/B（ Before value ）

  • STM Write registers to memory

• Stack addressing

  Replace the base address in multi register addressing with stack pointer register SP, And add {！}

  Note that it is full decreasing

• PC Relative addressing

  Short for relative addressing

  With PC Value is base address , The address label in the instruction is offset , Add the two together

  Cortex-M3/M4 Instruction set

  Data transfer instructions in the processor

• Register to register

• General registers and special registers

• Count to register immediately

Memory access instructions

This special exam will be given , There are too many instructions , skip

ah , sorry , The following is all about how to use instructions , skip , Next chapter