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        CALL FAR

        JMP FAR

        Stack switching process ：

        １． Using the... Of the object code snippet DPL To the current task TSS Select a stack , Including stack segment selector , Stack pointer

        ２． from TSS Read the selected segment selector , Stack pointer , And use the selector to read the stack segment descriptor ．

        ３． Check the privilege level of the stack segment descriptor , type ．

        ４． Temporarily save the current stack segment register SS And stack pointer ESP Content

        ５． Select the new stack segment , Stack pointer is substituted into SS and ESP register , Switch to new stack

        ６． Save what you just saved SS and ESP Content stack ．

        ７． According to the call gate descriptor " Number of parameters " instructions , Copy all parameters from the old stack to the new stack ．

        ８． Set the current register CS And instruction pointer registers EIP Press into the new stack ．

        ９． From the call gate descriptor, the target code segment selector and the in segment offset are passed to CS and EIP register , Start executing the called procedure ．

        Control return ：

        １． Check the stored in the stack CS The contents of the register , According to its RPL Decide whether to change the privilege level when returning

        ２． Read from the current stack CS and EIP The contents of the register , For code segment descriptors , Code segment selection sub RPL Field implements privilege level check ．

        ３． Such as far return with parameters , Put the parameters and ESP Add the current value of the register , To skip the parameter part of the stack ．

        ４． Such as when returning , You need to change the privilege level , From the stack SS and ESP Stack value is substituted into segment register SS and ESP． Switch to the caller's stack ．

        ５． If the far return instruction takes parameters , Put the parameters and ESP Add the current values

        ６． If you need to change the privilege level when returning , Check DS,ES,FS,GS Content ．

2. Task switching

        In real mode , Memory lowest address segment １KB It's the interrupt vector table ．

        In protected mode , The interrupt vector table is no longer used , Instead of , Interrupt descriptor table ． It stores the door descriptor , Including interrupt gate , Trap gate , Mission gate ．

        Call gate , From the local space of the task to the global space of higher privilege level ．

        Break the door , Trap gates allow interrupt handling within tasks , Move to the global space to perform some system level management ．

        When the interrupt occurs , The processor multiplies the interrupt number by 8 Access the interrupt descriptor table as an index ． When it finds that this is a task gate descriptor , I knew that task switching should be initiated ． therefore , It takes out the task gate descriptor ; Get the new task from the task gate descriptor TSS Chooser ; Reuse TSS Select sub access GDT, Take out the new task TSS The descriptor ．

        Go to the new task before execution , The processor saves the state of the current task first ．

        The processor accesses the new task TSS, Recover the contents of each register , Including general registers , Flag register , Segment register , Instruction pointer register , Stack pointer register , Local descriptor table register, etc ．

        Final , Task register TR Point to the new task TSS, And the processor immediately starts to perform new tasks ． Once the new task starts , The processor firmware will automatically TSS Descriptors B Location "1", Indicates that the status of the task is busy ．

        When the interruption occurs , Routine interrupt processing can be executed , You can also switch tasks ． They all use iret Command return ． One is to return different code segments within a task , One is to return to the interrupted task ．

        ３２ Bit processor EFLAGS Yes NT position , It means nested task flags ．

        For each task TSS There is a task link field , It can be filled in as TSS Descriptor selector ． Such as the current task EFLAGS The register of NT Is it "1", It means that the currently executing task is nested in other tasks , And can pass TSS The pointer of the task link field returns to the previous task ．

        When task switching is caused by interruption , Depends on whether the current task is nested within other tasks , Its EFLAGS The register of NT It may be "0", It could be "1"．

        The handling of new tasks is , We should take the old task TSS Select sub fill in the new task TSS Task link field in , At the same time, the new task EFLAGS The register of NT Location "1", To allow you to return to the previous task to continue ． meanwhile , Put the new task TSS Descriptors B Location "1"．

        use iret The instruction returns from the current task to the previous task , The premise is that the current task EFLAGS The register of NT The bit must be "1"． Whenever the processor encounters iret, It needs to check NT position , " ０, Indicates that it is a general interrupt process , Return processing according to the general interrupt ． namely , Interrupt returns are within the task ［ Although the interrupt processing process belongs to the operating system , But it belongs to the global space of the task ］; This bit is １, It indicates that the current task is being executed , Because of interrupting other tasks , so , You should return to the original interrupted task to continue ． here , The processor firmware puts the current task EFLAGS The register of NT Bit changed to "0", hold TSS Descriptors B Bit changed to "0"． After saving the current task status , With a new task TSS Restore the scene ．

        By remote CALL or JMP, Specify the of the task TSS Descriptor , It can also realize task switching ．

call 0x0010:0x00000000
jmp 0x0010:0x00000000

        When the processor executes these two instructions , First, use the descriptor given in the instruction to select the sub access GDT, Analyze its descriptor type ． If it is a code segment descriptor , According to the ordinary inter segment transfer rules ; If it is a call gate , Execute according to the call gate rule ; " TSS The descriptor , Or task gate , Then perform task switching ．

        The task gate descriptor can be installed in the interrupt descriptor table , It can also be installed in the global descriptor table or local descriptor table ．

        call Command initiated task switching , Current task TSS Descriptors B Bit keeps "1" unchanged ,EFLAGS Of NT No change ． Of new tasks TSS Of B Location "1",EFLAGS The register of NT The position is also set "1", Indicates that this task is nested in other tasks ． meanwhile ,TSS The content of the task link field is changed to that of the old task TSS Descriptor selector ．        

        

3. The operation of the processor during task switching

        The processor transfers control to other tasks in the following four ways ：

        １． Current procedure , The execution of a task or process transfers control to GDT One in TSS Descriptors jmp or call．

        ２． Current procedure , The execution of a task or process transfers control to GDT Or at present LDT Of a task gate descriptor in jmp or call Instructions ．

        ３． When an exception or interrupt occurs , The interrupt number points to the task gate in the interrupt descriptor table ．

        ４． stay EFLAGS The register of NT Under the position , The current task performed a iret．

        When the task switches , The processor does the following ：

        １． from jmp or call The operand of the instruction , Task gate or current task TSS Link fields to get new tasks TSS Descriptor selector ．

        ２． Check whether switching from current task to new task is allowed ． Privilege level check rules for data access apply to jmp and call． abnormal , interrupt ,［int n Except for ］ and iret Task switching caused by ignoring the target task gate or TSS Descriptors ＤＰＬ．int n The resulting interruption , To check DPL．

        ３．  Check for new tasks TSS Whether the descriptor has been marked as valid , And the boundary is also valid ．

        ４． Check if the new task is available , Not busy ［ Yes CALL,JMP, abnormal , Interrupt initiated task switching ］ Or busy , To iret Initiated task switching ．

        ５． Check the current task and the new task TSS, And the descriptors of the segments used by all tasks during task switching have been arranged in the system memory ．

        ６． Such as task switching by jmp or iret launch , The processor eliminates the busy flag of the current old task ; Such as by call Instructions , abnormal , Interrupt initiation , The busy flag remains ．

        ７． Such as task switching by iret launch , Processor setup EFLAGS A temporary copy of the register and clear it NT sign ; Such as by call, jmp, Initiated by an exception or interruption , Replica NT Flag unchanged ．

        ８． Save the status of the current task to its TSS in ． The processor finds the current... From the task register TSS The base address , Copy the status of the following registers to the current TSS in ： All general purpose registers , Segment selector in segment register , The one just now EFLAGS A copy of the register , And EIP．

        ９． Such as task switching by call Instructions , abnormal , Interrupt initiation , The processor loads... From the new task EFLAGS The register of NT Mark set ; Such as by iret or jmp Sponsored ,NT The status of the flag bit corresponds to that loaded from the new task EFLAGS The register of NT position ．

        １０． Such as task switching by call Instructions ,jmp Instructions , Initiated by an exception or interruption ． The processor will the new task TSS In the descriptor B Set up , Such as by iret Sponsored ,B The bit remains unchanged ．

        １１． With a new task TSS Select child and TSS Descriptor load task register TR．

        １２． Of new tasks TSS The status data is loaded into the processor ．

        １３． The descriptor corresponding to the segment selector is also loaded after verification ．

        １４． Start a new task

１６． Paging mechanism and dynamic page allocation

        Each segment descriptor has A position , Whenever a segment is accessed , The processor will set it ．

        A The reset of bit is timed by the operating system , It can take this opportunity to count the access frequency of the segment ．

        When there is not enough memory , It can swap out those less accessed segments to disk , To make room for the segment that is about to run ． Once a segment is moved to disk , The operating system should put its descriptor P A reset ． After a while , When this paragraph is visited again , Because of its descriptor P Is it "0", There is no exception in the segment thrown by the processor ［ Interrupt number １１］．

        It will use the same method to make room , Transfer the contents of this segment from disk to memory ． When this kind of interrupt returns , The processor will execute the instruction that caused the exception again ．

        Paging function , On the whole , It is to use pages with fixed length to replace segments with variable length ． The processor firmware does this , It can maximize speed and efficiency ．

16.1. Overview of paging mechanism

16.1.1. Simple paging model

        There are segment components in the processor that are responsible for segment management ．

        Each program or task has its own segment , These segments are defined with segment descriptors ． 

        Memory allocation involves segment space allocation and page allocation ．

        In paging mode , The operating system can create a common for all tasks 4GB Virtual memory space , You can also create separate for each task 4GB Virtual memory space ．

        When a program loads , The operating system should allocate segment space in the virtual memory on the left , And allocate the corresponding pages in the physical memory on the right ． therefore , The first step is to find free segment space , This space is not used by other programs , It is not used by other segments in the same program ．

        The minimum size of the page is 4KB． therefore ,8200 Byte segments need to occupy ３ A page ． If you allow page sharing , Multiple segments or programs can use the same page to store their own data ．

        After segmentation , The task of the operating system is to disassemble segments , Map to physical pages respectively ． Be careful , Segments must be continuous , However, the allocated pages are not required to be continuous , Next to each other ．

        Some programs close the page to recycle ． A few rounds down , Free pages are scattered in physical memory , Generally, it will not be continuous ． When assigning pages , The operating system will search the pages of the space , And assign it to the program to use , The total length of the allocated page should be greater than or equal to the segment length ．

        4GB Virtual memory space cannot be used to hold any data , Because it's virtual ． It is only used to indicate the memory usage ． When the operating system loads a program and creates it as a task , The operating system looks for free segments in virtual memory space , And map to free pages ． then , When you really start loading the program , Then split the data belonging to the segment according to the size of the page , Write to the corresponding page separately ．

        The output from the segment part is the linear address , Or virtual address ． To find the physical address of the page based on the linear address , The operating system needs to maintain a table , Convert a physical address into a physical address ．

        Here's the picture , Because there is 1048576 A page , So the conversion table also has 1048576 term ． Each item occupies ４ byte , The content is the physical address of the page ． Because the size of the page is 4KB, So the linear address is low 12 Bits can be used to access intra page offsets , high 20 Bits can be used to specify a physical page ． therefore , Put the high of the linear address 20 Bit as index , multiply 4, As the intra table offset , Take a double word from the table ． Get the physical address of the page corresponding to the linear address ．

        When the program loads , The operating system will first allocate segments in virtual memory ． then , How many pages are divided according to the paragraph , To search for free pages ． When the segment is large , Divide into several address sections according to the size of the page , The operating system uses the first address of each section , Take the height 20 position , multiply 4, Access the table as an offset , And write the physical address of the page allocated to the section into the table entry ． Last , Put the program data that needs to be written into each section , Write to the corresponding page ．

00

        Page memory management , The management and allocation of pages are independent , It has nothing to do with segmentation and segment address ． What the operating system should do , Is to find free pages , Assign it to the desired segment , And fill in the physical address of the page into the mapping table ．

        Linear address , Linear address space has nothing to do with the page allocation mechanism ．

        commonly , Every task can have 4GB Virtual memory space of ; meanwhile , Each task has its own page mapping table ．

        Although there are many tasks , Each task has its own 4GB Virtual memory space , but , In the whole system , Physical pages are uniformly deployed ． Consider a situation like this , Mission A There is a segment , The segment base address is 0x00050000, The segment length is 3000 byte , The operating system assigns it a physical address of 0x08001000 Page of ． After a while , Another task B To load the , It also has a segment , The segment base address is also 0x00050000, The segment length is 4096 byte ．

        At this point, the operating system is assigned a different , The physical address is 0x00700000 Page of ．

        In this case , On mission A Internal access linear address 0x00050006, What you visit is actually a physical address 0x08001006; On mission B When accessing the same linear address in , What you visit is actually a physical address 0x00700006．

        The operating system can retreat temporarily unused pages to disk , Call in the page that will be used soon , In this way, paging memory management can be realized ．

        above , It is the basic segment page memory management mechanism ．

16.1.2. Page directory , A page table , page

        4GB Virtual memory , Press 4KB Page division of , need 1048576 A page ． The actual starting position of the physical page of each page is 4 Byte storage , Then 4M Memory ．

        The main means of hierarchical paging structure is not to use a single mapping table , Replace page table of contents , A page table ．

        4GB Virtual memory corresponds to 1048576 individual 4KB Page of , Organize these pages in 1024 Page table , Each page table holds 1024 A page ． Each item in the page table accounts for 4 byte , The physical address of the storage page ． Therefore, the size of each page table 4KB, Occupy a page ．

        Inside the process , There is a control register CR3, The physical address where the current task page directory is stored , so , Also called page directory base register ．

        Each task has its own TSS．

        Page directory , The page table is also an ordinary page , Mixed in all physical pages ． They differ from ordinary pages only in their functions ． When the mission is cancelled , They will be recycled just like ordinary pages occupied by tasks , And assigned to other tasks ．

16.1.3. The specific process of address transformation

        CR3 The Register gives the physical base address of the page directory ; The page directory gives the physical addresses of all page tables , Each page table gives the physical address of the pages it contains ．

        Paging mechanism , In the previous protection mode , Segment base address + Segment offset gets the virtual address ． Only after the conversion of page parts can we get the physical address ．

        The page unit of the processor is specially responsible for the conversion from linear address to physical address ． It first sent the segment components 32 The bit linear address is truncated to ３ paragraph , The difference is high 10 position , middle 10 position , low 12 position ． high 10 Bit is the page directory index , middle 10 Bit is the index of the page table , low 12 Bits are used as intra page offsets ．

        Be careful , This transformation is not without reason , It's arranged in advance ． When the task is loaded , The operating system first creates a virtual segment , And according to the height of the segment address 20 Bit determines which page directory entries and page table entries it needs ． then , Find free pages , Write the data that should be written in the segment to one or more pages , And fill in the physical address of the page into the corresponding page table item ． Only in this way , When the program is running , Address transformation can be carried out in reverse order , Find the right data ．

16.3 Make the kernel work under the paging mechanism

16.3.1. Create the page directory table and page table of the kernel

        First enter the protected mode to execute the kernel program , Let the kernel work under the paging mechanism ．

        Ready to open the page function , First, you must create a page directory and page table ． Each task has its own page directory and page table ． Although the kernel is common to all tasks , No exception ． For the kernel to work properly , You must create its own page directory , A page table ．

        In an ideal paging system , To load the program , You need to search the available pages first , And map them to segments ． In this case , The linear address output by the segment part is different from the physical address output by the page part , It's natural ． 

        Because everything happens after the program is loaded , After the segment and page have a clear mapping relationship ． In this case , After the page function is turned on , All aspects can be well adapted ．

        The kernel is loaded before the page function is turned on , The position of the segment in memory has been fixed ． At this time , Even if the page function is turned on , The linear address also needs to be the same as the physical address ．

        Be careful , After entering paging mode , The address of everything becomes a linear address ．

        Because our instance kernel is very small , Therefore, only the low-end 1M Memory special processing , Make the linear address of this part of memory the same as the physical address after page part conversion ．

        For our instance kernel , Just one page table is enough ．

        In the page directory and page table , Only the height of the page table or page physical address is saved 20 position ． In this case , Can only care about high 20 position , low 12 Bit arrangement for other purposes ．

        Control register CR0 At the top of the table , It's a bit 31, yes PG position , Used to turn the page function on or off ． When this bit is cleared , Page function is turned off , The linear address from the segment component is the physical address ; When it is set , Page function is enabled ． The page function can only be enabled in protected mode ．

        After opening , Address generated by segment part , To be sent to page parts for Exchange , To get the real physical address ．

16.3.2. Page mapping of global space and local space of the task

        Each task has its own page table of contents , A page table , When the task is created , They are created together ． When the task is executed , Page parts use them to access the private memory space of the task itself ． Page directory table of tasks , The page table cannot contain only the private pages of the task ．

        Mission 4GB The address space consists of two parts ： Local space , Global space , The global space is shared by all tasks ． The kernel is shared by all tasks , It should belong to the global space of each task ．

        commonly , For the sake of fairness , The global address space occupies the task 4GB The height of the address space 2GB, The corresponding linear address range is ：0x80000000~0xFFFFFFFF; Local address space usage is low 2GB, The corresponding linear address range is ：0x00000000~0x7FFFFFFF．

        In any task , At any time , For example, the linear address sent by the segment part is higher than or equal to 0x80000000, Point to and access the global address space , Or the kernel ．

        So , To modify the kernel's own page directory table , Even descriptors of various segments of the kernel , Move the kernel to the high end of the virtual address space , from 0x80000000 A continuous area at the beginning ．

16.4. Create kernel tasks