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Verilog 每日一题 (VL5 信号发生器)
2022-07-28 16:23:00 【别再出error了】
题目描述:
请编写一个信号发生器模块,根据波形选择信号wave_choise发出相应的波形:wave_choice=0时,发出方波信号;wave_choice=1时,发出锯齿波信号;wave_choice=2时,发出三角波信号。

有一说一,牛客网现在的verilog的题出的就挺离谱,不看答案题目都不知道啥意思.
解题思路:
这一题首先需要确定如何得到三种信号,以及最基本的三种信号的幅值、周期,题目里全都没有。从答案可以看出,方波周期为20个clk,且占空比为0.5,锯齿波周期为21个clk,三角波周期为40个clk。
具体详解如下:
`timescale 1ns/1ns
module signal_generator(
input clk,
input rst_n,
input [1:0] wave_choise,
output reg [4:0]wave
);
//wave_choice 为0时输出方波,先写出方波信号发生器
//以20个clk为方波周期(题目没有,看答案才知道),则需要一个计数器num
reg [4:0] num;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
num<=0;
else if(wave_choise==0)
num <=(num==19)? 0:num+1;
else
num <= 0;
//wave <=(num>9)? 20:0; //10-19取高电平,0-9取低电平
end
//wave_choice=1时,为锯齿波信号,周期为21个clk
//wave <=(wave==20)? 0:wave+1; 到20跳0;
//wave_choice=2时,为三角波信号,周期为40
//一开始思路:再添加一个num0进行计数,0-19下降,20-39上升,忽略了初始值并不是0或20;判断条件没有明确;应该需要设置一个方向变量dir ;
reg dir;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
dir<=0;
//else if(wave_choise==2) num0 <= (num0==39)? 0:num0+1;
//else num0 <= 0; 一开始的计数的方法不合适
else if(wave_choise==2)
dir <= (wave==1)? 1:(wave==19)? 0: dir;
//值得注意的是,取1时和19时进行翻转,并不是在0和20处翻转,因为wave的是非阻塞赋值
else
dir <=0;
end
//最后进行wave_choise的判断
always @(posedge clk or negedge rst_n) begin
if(!rst_n) wave<=0;
else
case(wave_choise)
0: wave <=(num==9)? 20:(num==19)? 0 :wave ;
1: wave <=(wave==20)? 0:wave+1; //锯齿波
2: wave<=(~dir)? wave-1 :wave+1 ;
default: wave<=0;
endcase
end
endmodule易错:在上述代码最后一个模块中,判断条件需要好好考虑
//一开始写的判断条件是num>9时wave=20;使得上升慢了一拍,因为num=10时才变高电平,此时已经技术了11个周期了,。应该在num==9是变高电平,num是非阻塞赋值
//同理,对于低电平的判断也不是num=0时发生跳变,这也会导致慢了一拍,需要注意的是,若采用阻塞赋值,用0: wave <=(num>9)? 20:0 ; 判断是没有问题的。
阻塞赋值和非阻塞赋值在这一题需要很注意!

纪念第一次牛客网做题做崩了哈哈哈
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