当前位置：网站首页>[HDLBits brush questions] Verilog Language (4) Procedures and More Verilog Features section

本篇博客对 Verilog Language The questions for the remaining two sections are completed,The key is to read the question first,Then think about how to implement and verify,Here we use the first interpretation of the topic,That is to tell us what to do,Then give the answer directly.

Procedures

Alwaysblock1

分别用 assign 语句和 always @(*) The block statement implements the AND gate operation.

module top_module(
    input        a, 
    input        b,
    output wire  out_assign,
    output reg   out_alwaysblock
);

assign out_assign = a & b;

always @(*) begin
	out_alwaysblock = a & b;
end

endmodule

Alwaysblock2

连续赋值（assign x = y;）.不能在 always 块中使用.
Procedure blocking assignment：（x = y;）.Can only be used in the process.
Procedure non-blocking assignment：（x <= y;）.Can only be used in the process.
在组合 always 块中,使用阻塞赋值.
在时序 always 块中,使用非阻塞赋值.

module top_module(
    input        clk,
    input        a,
    input        b,
    output wire  out_assign,
    output reg   out_always_comb,
    output reg   out_always_ff  
);

assign out_assign = a ^ b;

always @(*) begin
	out_always_comb = a ^ b;
end

always @(posedge clk) begin
	out_always_ff <= a ^ b;
end

endmodule

Always if

if 语句通常创建一个 2 对 1 多路复用器,如果条件为 ture,则选择一个输入,如果条件为 false,则选择另一个输入.This is equivalent to using continuous assignment with the conditional operator：
assign out = (condition) ? x : y;
构建一个在 a 和 b 之间进行选择的 2 对 1 多路复用器.如果sel_b1和sel_b2都为真,请选择 b.否则,请选择 a.Do the same operation twice,Use assignment statements and procedures, respectively if 语句.

module top_module(
    input        a,
    input        b,
    input        sel_b1,
    input        sel_b2,
    output wire  out_assign,
    output reg   out_always   
); 

assign out_assign = (sel_b1 & sel_b2) ? b : a;

always @(*) begin
	if (sel_b1 & sel_b2) begin
		out_always = b;
	end
	else begin
		out_always = a;
	end
end

endmodule

Always if2

Learn how to avoid spawning latch, 比如在 always The cases listed in the block are not complete,There will be situations that you did not list,What would the output be？Verilog的答案是：保持输出不变.这种“保持输出不变”的行为意味着需要记住当前状态,从而产生latch.Combinatorial logic cannot save any state.A combinational circuit must assign a value to all outputs under all conditions.This usually means that the output always needs to be allocated else clause or default value.

module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated) begin
            shut_off_computer = 1;
        end
        else begin
           	shut_off_computer = 0;
        end   
    end

    always @(*) begin
        if (~arrived) begin
            keep_driving = ~gas_tank_empty;	
        end
        else begin
        	keep_driving = 0;
        end
    end

endmodule

Always case

case语句的练习.case 语句以 case 开头,每个“case 项”Both end with a colon.
Only one statement can be executed per case item.这意味着,If multiple statements are required,则必须使用begin结束.允许重复（and partially overlap）案例项目.使用第一个匹配的.
在本练习中,创建一个 6 对 1 多路复用器.当 sel 介于 0 和 5 之间时,选择相应的数据输入.否则,输出 0.数据输入和输出均为4位宽.

module top_module ( 
    input      [2:0]   sel, 
    input      [3:0]   data0,
    input      [3:0]   data1,
    input      [3:0]   data2,
    input      [3:0]   data3,
    input      [3:0]   data4,
    input      [3:0]   data5,
    output reg [3:0]   out   
);

    always @(*) begin  
        case(sel)
        	0: out = data0;
        	1: out = data1;
        	2: out = data2;
        	3: out = data3;
        	4: out = data4;
        	5: out = data5;
      default: out = 0;
        endcase
    end

endmodule

Always case2

优先级编码器是一种组合电路,When given an input bit vector,The first one in the output vector1位的位置.例如,给定输入 8'b100 1 0000 的 8 位优先级编码器将输出 3'd4,因为 bit[4] 是第一个高位.构建 4 位优先级编码器.对于此问题,If the input bits are all zero,则输出为零.请注意,4 位数字有 16 种可能的组合.

module top_module (
    input      [3:0]  in,
    output reg [1:0]  pos  
);

always @(*) begin
	case(in)
		4'b0000: pos = 0;
		4'b0001: pos = 0;
		4'b0010: pos = 1;
		4'b0100: pos = 2;
		4'b1000: pos = 3;
		4'b0011: pos = 0;
		4'b0110: pos = 1;
		4'b1100: pos = 2;
		4'b0101: pos = 0;
		4'b1010: pos = 1;
		4'b1001: pos = 0;
		4'b0111: pos = 0;
		4'b1110: pos = 1;
		4'b1011: pos = 0;
		4'b1101: pos = 0;
		4'b1111: pos = 0;
	endcase
end

endmodule

Always casez

case Statements are like checking each case in order,This is a big combinatorial logic function.请注意,某些输入（例如,4'b1111）How multiple case items will be matched.选择第一个匹配项（因此 4'b1111 matches the first item,out = 0,But none of the latter ones match）.还有一个类似的案例,它将x和z视为不在乎.I can't see it therecasezhow much sense it makes to use it.数字？是 z 的同义词.所以 2'bz0 与 2'b？0 相同.

module top_module (
    input      [7:0]  in,
    output reg [2:0]  pos  
);

always @(*) begin
	casez(in)
		8'bzzzzzzz1: pos = 0;   //zIndicates that it doesn't care what the value is.It is only necessary to satisfy the condition of the latter bit
		8'bzzzzzz10: pos = 1;
		8'bzzzzz100: pos = 2;
		8'bzzzz1000: pos = 3;
		8'bzzz10000: pos = 4;
		8'bzz100000: pos = 5;
		8'bz1000000: pos = 6;
		8'b10000000: pos = 7;
	endcase
end

endmodule

Always nolatches

在使用casestatement to avoid generatinglatch的方法.
To avoid generating latches,All outputs must be assigned a value under all possible conditions.Just having a default case is not enough.All four outputs in all four cases must be assigned a value,and assigns a value by default.This can involve a lot of unnecessary typing.
One way to fix this is in caseAssign one to the output before the statement“默认值”：
always @(*) begin
up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
case (scancode)
... // Set to 1 as necessary.
endcase
end
This style of code ensures that the output is assigned a value in all possible cases,除非caseStatement override assignment.
提醒：A logic synthesizer generates a combinational circuit,Its behavior is equivalent to that described by the code.Hardware is not in order“执行”代码行.

module top_module (
    input [15:0]  scancode,
    output reg    left,
    output reg    down,
    output reg    right,
    output reg    up  
); 

always @(*) begin
	up    = 1'b0;
	down  = 1'b0;
	left  = 1'b0;
	right = 1'b0;
	case(scancode)
        16'he075: up    = 1'b1;
        16'he072: down  = 1'b1;
        16'he06b: left  = 1'b1;
        16'he074: right = 1'b1;
        default: begin
        		  up    = 1'b0;
				  down  = 1'b0;
				  left  = 1'b0;
				  right = 1'b0;
        end	
	endcase
end

endmodule

More Verilog Features

Conditional

给定四个无符号数字,找到最小值.无符号数字可以与标准比较运算符（a < b）进行比较.Use conditional operators to make bidirectional minimal circuits,Then combine several of them to create 4 minimum circuit.Some wire vectors may be needed as intermediate results.

module top_module (
    input  [7:0]  a, b, c, d,
    output [7:0]  min
);
wire  [7:0]  smaller0;
wire  [7:0]  smaller1;
wire  [7:0]  smaller2;

assign smaller0 = (a > b)? b : a;
assign smaller1 = (c > d)? d : c;
assign smaller2 = (smaller0 > smaller1)? smaller1 : smaller0;
assign min = smaller2;

endmodule

注：It can also be designed in the form of an assembly line,The design method of pipeline can make the operating speed of the system increase.

Reduction

Parity checking is often used as a simple way to detect errors when transmitting data over imperfect channels.创建一个电路,该电路将计算 8 位字节的奇偶校验位（This will add th to that byte 9 位）.将使用“偶数”奇偶校验,Parity bits are just all8个数据位的XOR.

A simple XOR of consecutive bits.

module top_module (
    input [7:0]  in,
    output       parity
); 

assign parity = ^in;

endmodule

Gates100

在[99：0]built in has100个输入的组合电路.
有 3 个输出：

out_and：输出100输入与门 &.
out_or：100 输入 OR 门 | 的输出.
out_xor：100 输入异或门 ^ 的输出.

module top_module( 
    input  [99:0]  in,
    output         out_and,
    output         out_or,
    output         out_xor 
);

assign out_and = & in;
assign out_or = | in;
assign out_xor = ^ in;

endmodule

Vector100r

给定一个 100 位输入向量 [99：0],反转其位排序.

module top_module( 
    input  [99:0]  in,
    output [99:0]  out
);
	integer i;
	always @(*) begin
		for (i=0;i<100;i=i+1) begin
			out[i] = in[99-i];
		end		
	end
endmodule

Popcount255

For the input bit width is 255The number of , and its bits are calculated as 1 的个数并输出

module top_module( 
    input  [254:0]  in,
    output [7:0]    out 
);

reg [7:0] cnt;
integer i;
always @(*) begin
	cnt = 'd0;
	for (i=0;i<255;i=i+1) begin
		cnt = (in[i])? (cnt+1'b1):cnt;
	end
end
assign out = cnt;

endmodule

Adder100i

通过实例化 100 a full adder to create one 100 Bit binary traveling wave carry adder.加法器将两个 100 A digit number and a portable number are added,以产生 100 位总和并执行.Actual instantiation of the full adder,Also executed from each full adder output in the traveling-carry adder.cout[99]is the final execution of the last full adder.

Note the special case when computing the first full adder.

module top_module( 
    input  [99:0]  a, b,
    input          cin,
    output [99:0]  cout,
    output [99:0]  sum 
);
	genvar i;
    generate
        for(i=0;i<100;i=i+1) begin:adder
            if(i==0)
                assign{cout[0],sum[0]}=a[0]+b[0]+cin;
            else
                assign{cout[i],sum[i]}=a[i]+b[i]+cout[i-1];
        end           
    endgenerate
    
endmodule

Bcdadd100

with a four-bit full adder block,Calculates the addition of two input data,其位宽为400.

在这里吐槽一下 HDLBits The built-in compiler is a bit neurotic,Some unnecessary details are over-controlled,And some tricky syntaxes are not supported...

module top_module( 
    input  [399:0]  a,b,
    input           cin,
    output          cout,
    output [399:0]  sum 
);

wire [99:0]  cin_cnt;
genvar i;
generate
	for (i=0;i<100;i=i+1) begin:test
		if (i == 0) begin
			bcd_fadd bcd_fadd_inst(a[3:0],b[3:0],cin,cin_cnt[0],sum[3:0]);
		end
		else begin
			bcd_fadd bcd_fadd_inst(a[4*(i+1)-1:4*i],b[4*(i+1)-1:4*i],cin_cnt[i-1],cin_cnt[i],sum[4*(i+1)-1:4*i]);
		end
		
	end
	assign cout = cin_cnt[99];
endgenerate

endmodule

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