FPGA - odd even frequency division and decimal frequency division code routine

1.  Even frequency division

     Even frequency division is relatively simple , Just note that the condition for the clock to flip is (N/2) still (N/2)-1, The non blocking assignment will not update the value until the next clock .   

2.  Odd frequency division

     Odd frequency division is more complicated than even frequency division , When the duty cycle of frequency division is not required , Input clock clk Rising edge count , You can set the flip point of two counts , One is (N-1)/2, One is (N-1), Count to (N-1) The output clock flips and the counter is cleared , Suppose the counter counts 0~(N-1)/2 Interval output low level , Then the low level of the output clock has (N-1)/2 + 1 individual clk cycle , The count of high level is (N-1)/2+1 ~ (N-1), common (N-1)/2 individual clk cycle , So it's not 50% Duty cycle .

     When the required duty cycle is 50% when , Input clock clk The rising and falling edges of are counted separately , According to the two counters, two clocks with staggered output are obtained , Make two clocks “ or ” operation , A clock that can make up for the difference , achieve 50% Duty cycle . With 7 Take frequency division as an example , The code is as follows ：

module Odd_Divider(         inputclk,         inputrst_n,         outputclk_divider); reg [2:0] count_p;    // Rising edge count reg [2:0] count_n;    // Falling edge count reg clk_p;                   // Rising edge frequency division reg clk_n;                   // Falling edge frequency division  // Rising edge count always