当前位置：网站首页>VHDL programming experiment exercises collection
VHDL programming experiment exercises collection
2022-06-12 23:53:00 【Goose feather is on the way】
1. Complete corresponding functions as required .
Design 6 Bit binary adder , The frequency of the adder is 1Hz, Perform download test , Record test results .
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
PORT(INCLK: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC_VECTOR(5 DOWNTO 0)); --6 Bit binary
END CNT6;
ARCHITECTURE ARCH_CNT6 OF CNT6 IS
SIGNAL FP: STD_LOGIC_VECTOR(24 DOWNTO 0);
SIGNAL F: STD_LOGIC;
SIGNAL Q: STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
PROCESS(INCLK)
BEGIN
IF(INCLK'EVENT AND INCLK='1')THEN
IF FP=24999999 THEN -- frequency division 1Hz
FP<=(OTHERS=>'0');
F<=not F;
else FP<=FP+1;
end if;
end if;
end process;
process(F)
begin
if (F'event and f='1') then
Q<=Q+1; -- Hardware connection 6 individual LED
end if;
end process;
OUTPUT<=Q;
end ARCH_CNT6;
2. Complete corresponding functions as required .
Design 4 Bit binary adder , The frequency of the adder is 0.25Hz, Perform download test , Record test results .
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4 IS
PORT(INCLK: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --4 Bit binary
END CNT4;
ARCHITECTURE ARCH_CNT4 OF CNT4 IS
SIGNAL FP: STD_LOGIC_VECTOR(26 DOWNTO 0);
SIGNAL F: STD_LOGIC;
SIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(INCLK)
BEGIN
IF(INCLK'EVENT AND INCLK='1')THEN
IF FP= 99999999 THEN -- frequency division 0.25Hz
FP<=(OTHERS=>'0');
F<=not F;
else FP<=FP+1;
end if;
end if;
end process;
process(F)
begin
if (F'event and f='1') then
Q<=Q+1; -- Hardware connection 4 individual LED
end if;
end process;
OUTPUT<=Q;
end ARCH_CNT4;
3. Complete corresponding functions as required .
Design 4 Bit flow lamp program , The flow frequency is 1Hz, Perform download test , Record test results .
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED1 IS
PORT(INCLK: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --2 Bit binary representation 4 States
END LED1;
ARCHITECTURE ARCH_LED1 OF LED1 IS
SIGNAL FP: STD_LOGIC_VECTOR(24 DOWNTO 0);
SIGNAL F: STD_LOGIC;
SIGNAL Q: STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
PROCESS(INCLK)
BEGIN
IF(INCLK'EVENT AND INCLK='1')THEN
IF FP= 24999999 THEN -- frequency division 1Hz
FP<=(OTHERS=>'0');
F<=not F;
ELSE FP<=FP+1;
END IF;
END IF;
END PROCESS;
PROCESS(F) --Q For counting
BEGIN
IF (F'event and f='1') then
Q<=Q+1;
END IF;
END PROCESS;
PROCESS(Q) -- Running water lamp process
BEGIN
CASE Q IS
WHEN "00" => OUTPUT <= "1110";
WHEN "01" => OUTPUT <= "1101";
WHEN "10" => OUTPUT <= "1011";
WHEN "11" => OUTPUT <= "0111";
--WHEN "00" => OUTPUT <= "0111";
--WHEN "01" => OUTPUT <= "1011";
--WHEN "10" => OUTPUT <= "1101";
--WHEN "11" => OUTPUT <= "1110";
END CASE;
END PROCESS;
end ARCH_LED1;
4. Complete corresponding functions as required .
Design 4 Bit flow lamp program , The flow frequency is 0.25Hz, Perform download test , Record test results .
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED2 IS
PORT(INCLK: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --2 Bit binary representation 4 States
END LED2;
ARCHITECTURE ARCH_LED2 OF LED2 IS
SIGNAL FP: STD_LOGIC_VECTOR(26 DOWNTO 0);
SIGNAL F: STD_LOGIC;
SIGNAL Q: STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
PROCESS(INCLK)
BEGIN
IF(INCLK'EVENT AND INCLK='1')THEN
IF FP= 99999999 THEN -- frequency division 0.25Hz
FP<=(OTHERS=>'0');
F<=not F;
ELSE FP<=FP+1;
END IF;
END IF;
END PROCESS;
PROCESS(F) --Q For counting
BEGIN
IF (F'event and f='1') then
Q<=Q+1;
END IF;
END PROCESS;
PROCESS(Q) -- Running water lamp process
BEGIN
CASE Q IS
WHEN "00" => OUTPUT <= "1110";
WHEN "01" => OUTPUT <= "1101";
WHEN "10" => OUTPUT <= "1011";
WHEN "11" => OUTPUT <= "0111";
--WHEN "00" => OUTPUT <= "0111";
--WHEN "01" => OUTPUT <= "1011";
--WHEN "10" => OUTPUT <= "1101";
--WHEN "11" => OUTPUT <= "1110";
END CASE;
END PROCESS;
end ARCH_LED2;
5. Complete corresponding functions as required .
Use text input method to design a 12 return 1 circuit , And carry out functional test , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity T12TO1 is
port(finclk:in std_logic;
outputa:out std_logic_vector(7 downto 0);
outputb:out std_logic_vector(7 downto 0));
end T12TO1;
architecture arch_T12TO1 of T12TO1 is
signal sa,sb:std_logic_vector(3 downto 0);
signal f:std_logic;
component fp
port(inclk:in std_logic;
outputa:out std_logic);
end component;
begin
u1:fp port map(finclk,f);
process(f)
begin
if(rising_edge(f)) then
if(sa=2 and sb=1) then
sa<="0001";
sb<="0000";
else
if sa=9 then
sa<="0000";
sb<=sb+1;
else
sa<=sa+1;
end if;
end if;
end if;
end process;
with sa select
outputa<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
with sb select
outputb<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
end architecture arch_T12TO1;
6. Complete corresponding functions as required .
Use text input method to design a 59 return 0 circuit , And carry out functional test , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity T59TO0 is
port(finclk:in std_logic;
outputa:out std_logic_vector(7 downto 0);
outputb:out std_logic_vector(7 downto 0));
end T59TO0;
architecture arch_T59TO0 of T59TO0 is
signal sa,sb:std_logic_vector(3 downto 0);
signal f:std_logic;
component fp
port(inclk:in std_logic;
outputa:out std_logic);
end component;
begin
u1:fp port map(finclk,f);
process(f)
begin
if(rising_edge(f)) then
if(sa=9 and sb=5) then
sa<="0000";
sb<="0000";
else
if sa=9 then
sa<="0000";
sb<=sb+1;
else
sa<=sa+1;
end if;
end if;
end if;
end process;
with sa select
outputa<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
with sb select
outputb<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
end architecture arch_T59TO0;
Use text input method to design a 23 return 0 circuit , And carry out functional test , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity T23TO0 is
port(finclk:in std_logic;
outputa:out std_logic_vector(7 downto 0);
outputb:out std_logic_vector(7 downto 0));
end T23TO0;
architecture arch_T23TO0 of T23TO0 is
signal sa,sb:std_logic_vector(3 downto 0);
signal f:std_logic;
component fp
port(inclk:in std_logic;
outputa:out std_logic);
end component;
begin
u1:fp port map(finclk,f);
process(f)
begin
if(rising_edge(f)) then
if(sa=3 and sb=2) then
sa<="0000";
sb<="0000";
else
if sa=9 then
sa<="0000";
sb<=sb+1;
else
sa<=sa+1;
end if;
end if;
end if;
end process;
with sa select
outputa<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
with sb select
outputb<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
end architecture arch_T23TO0;
8. Complete corresponding functions as required .
Use text input method to design a 7 return 4 circuit , Display with a digital tube , And carry out functional test , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity T7TO4 is
port(finclk:in std_logic;
outputa:out std_logic_vector(7 downto 0);
outputb:out std_logic_vector(7 downto 0));
end T7TO4;
architecture arch_T7TO4 of T7TO4 is
signal sa,sb:std_logic_vector(3 downto 0);
signal f:std_logic;
component fp
port(inclk:in std_logic;
outputa:out std_logic);
end component;
begin
u1:fp port map(finclk,f);
process(f)
begin
if(rising_edge(f)) then
if(sa=7 and sb=0) then
sa<="0100";
sb<="0000";
else
if sa=9 then
sa<="0000";
sb<=sb+1;
else
sa<=sa+1;
end if;
end if;
end if;
end process;
with sa select
outputa<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
with sb select
outputb<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
end architecture arch_T7TO4;
9. Complete corresponding functions as required , Record test results .
Design a clock circuit with text input method , from 4 A dynamic digital tube analog display 、 The process of counting minutes .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter9 is
port(inclk: in std_logic;
outseg: out std_logic_vector(7 downto 0); -- Segment selection
outbit: out std_logic_vector(3 downto 0)); -- Biting
end counter9;
Architecture a_counter9 of counter9 is
signal ma,mb,mc,md,me,mf,mseg:std_logic_vector(3 downto 0);
signal lm,hm:std_logic_vector(12 downto 0);
signal fpa,fpb:std_logic;
signal st:std_logic_vector(1 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk='1')then
if lm=1249 then -- Frequency division counting
lm<=(others => '0');fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if hm=1249 then
hm<=(others => '0');fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
process(fpb)
begin
if(fpb'event and fpb='1')then
if ma=9 then -- Minutes a bit ,59 return 0
ma<="0000";
if mb=5 then
mb<="0000";
if(mc=2 and md=1)then --12 return 1 Hours
mc<="0001";md<="0000";
else
if mc=9 then
md<=md+1;mc<="0000";
else
mc<=mc+1;
end if;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
st<=st+1;
end if;
end process;
process(st)
begin
case st is
when "00"=> --min
mseg<=ma;
outbit<="1110";
when "01"=>
mseg<=mb;
outbit<="1101";
when "10"=> --hour
mseg<=mc;
outbit<="1011";
when "11"=>
mseg<=md;
outbit<="0111";
when others=>
outbit<="1111";
end case;
end process;
with mseg select
outseg<= "01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"00000010" when "1111", -- Show g paragraph , Used for dividing the nixie tube display
"11111100" when others; -- Abnormal state
end a_counter9;
10. Complete corresponding functions as required , Record test results .
Design a clock circuit with text input method , from 5 A dynamic digital tube analog display 、 The process of counting minutes , Time division “-” interval .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter10 is
port(inclk: in std_logic;
outseg: out std_logic_vector(7 downto 0); -- Segment selection
outbit: out std_logic_vector(4 downto 0)); -- Biting
end counter10;
Architecture a_counter10 of counter10 is
signal ma,mb,mc,md,mseg:std_logic_vector(3 downto 0);
signal lm,hm:std_logic_vector(12 downto 0);
signal fpa,fpb:std_logic;
signal st:std_logic_vector(2 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk='1')then
if lm=1249 then -- Frequency division counting
lm<=(others => '0');fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if hm=1249 then
hm<=(others => '0');fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
process(fpb)
begin
if(fpb'event and fpb='1')then
if ma=9 then -- Minutes a bit ,59 return 0
ma<="0000";
if mb=5 then
mb<="0000";
if(mc=2 and md=1)then --12 return 1 Hours
mc<="0001";md<="0000";
else
if mc=9 then
md<=md+1;mc<="0000";
else
mc<=mc+1;
end if;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
st<=st+1;
end if;
end process;
process(st)
begin
case st is
when "000"=> --min
mseg<=ma;
outbit<="11110";
when "001"=>
mseg<=mb;
outbit<="11101";
when "010"=>
mseg<="1111"; --g paragraph
outbit<="11011";
when "011"=> --hour
mseg<=mc;
outbit<="10111";
when "100"=>
mseg<=md;
outbit<="01111";
when others=>
outbit<="11111";
end case;
end process;
with mseg select
outseg<= "01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"00000010" when "1111", -- Show g paragraph , Used for dividing the nixie tube display
"11111100" when others; -- Abnormal state
end a_counter10;
11. Complete corresponding functions as required , Record test results .
Design a clock circuit with text input method , from 6 A dynamic digital tube analog display 、 branch 、 Second timing process .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter11 is
port(inclk: in std_logic;
outseg: out std_logic_vector(7 downto 0); -- Segment selection
outbit: out std_logic_vector(5 downto 0)); -- Biting
end counter11;
Architecture a_counter11 of counter11 is
signal ma,mb,mc,md,me,mf,mseg:std_logic_vector(3 downto 0);
signal lm,hm:std_logic_vector(12 downto 0);
signal fpa,fpb:std_logic;
signal st:std_logic_vector(2 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk='1')then
if lm=1249 then -- Frequency division counting
lm<=(others => '0');fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if hm=1249 then
hm<=(others => '0');fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
process(fpb)
begin
if(fpb'event and fpb='1')then
if mf=9 then -- Minutes a bit ,59 return 0
mf<="0000";
if me=5 then
me<="0000";
if ma=9 then -- Minutes a bit ,59 return 0
ma<="0000";
if mb=5 then
mb<="0000";
if(mc=2 and md=1)then --12 return 1 Hours
mc<="0001";md<="0000";
else
if mc=9 then
md<=md+1;mc<="0000";
else
mc<=mc+1;
end if;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
end if;
else
me<=me+1;
end if;
else
mf<=mf+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
st<=st+1;
end if;
end process;
process(st)
begin
case st is
when "000"=> --sec
mseg<=mf;
outbit<="111110";
when "001"=>
mseg<=me;
outbit<="111101";
when "010"=>
mseg<=ma; --min
outbit<="111011";
when "011"=>
mseg<=mb;
outbit<="110111";
when "100"=> --hour
mseg<=mc;
outbit<="101111";
when "101"=>
mseg<=md;
outbit<="011111";
when others=>
outbit<="111111";
end case;
end process;
with mseg select
outseg<= "01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"00000010" when "1111", -- Show g paragraph , Used for dividing the nixie tube display
"11111100" when others; -- Abnormal state
end a_counter11;
12. Complete corresponding functions as required , Record test results .
Design a clock circuit with text input method , from 8 A dynamic digital tube analog display 、 branch 、 Second timing process , Minutes and seconds “-” interval .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(inclk: in std_logic;
outseg: out std_logic_vector(7 downto 0); -- Segment selection
outbit: out std_logic_vector(7 downto 0)); -- Biting
end counter;
Architecture a_counter of counter is
signal ma,mb,mc,md,me,mf,mseg:std_logic_vector(3 downto 0);
signal lm,hm:std_logic_vector(12 downto 0);
signal fpa,fpb:std_logic;
signal st:std_logic_vector(3 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk='1')then
if lm=1249 then -- Frequency division counting
lm<=(others => '0');fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if hm=1249 then
hm<=(others => '0');fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
process(fpb)
begin
if(fpb'event and fpb='1')then
if mf=9 then -- Second bit ,59 return 0
mf<="0000";
if me=5 then
me<="0000";
if ma=9 then -- Minutes a bit ,59 return 0
ma<="0000";
if mb=5 then
mb<="0000";
if(mc=2 and md=1)then --12 return 1 Hours
mc<="0001";md<="0000";
else
if mc=9 then
md<=md+1;mc<="0000";
else
mc<=mc+1;
end if;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
end if;
else
me<=me+1;
end if;
else
mf<=mf+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
st<=st+1;
end if;
end process;
process(st)
begin
case st is
when "0000"=>
mseg<=mf; --sec
outbit<="11111110";
when "0001"=>
mseg<=me; --sec
outbit<="11111101";
when "0010"=>
mseg<="1111"; --g
outbit<="11111011";
when "0011"=> --min
mseg<=ma;
outbit<="11110111";
when "0100"=>
mseg<=mb;
outbit<="11101111";
when "0101"=>
mseg<="1111"; --g
outbit<="11011111";
when "0110"=> --hour
mseg<=mc;
outbit<="10111111";
when "0111"=>
mseg<=md;
outbit<="01111111";
when others=>
outbit<="11111111";
end case;
end process;
with mseg select
outseg<= "01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"00000010" when "1111", -- Show g paragraph , Used for dividing the nixie tube display
"11111100" when others; -- Abnormal state
end a_counter;
13. Complete corresponding functions as required .
Use text input method to design a 4 position BCD Code conversion circuit , Download and test , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bcdconvert4 is
port(ina:in std_logic_vector(3 downto 0);
inclk:in std_logic;
outseg: out std_logic_vector(7 downto 0);
outbit: out std_logic_vector(1 downto 0));
end bcdconvert4;
architecture arch_bcdconvert4 of bcdconvert4 is
signal sina:std_logic_vector(3 downto 0);
signal souta,soutb:std_logic_vector(3 downto 0);
signal ssouta,ssoutb:std_logic_vector(3 downto 0);
signal outa,outc,outb:std_logic_vector(7 downto 0);
signal lm:std_logic_vector(12 downto 0);
signal fpa:std_logic;
signal st:std_logic_vector(1 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk ='1')then
if lm = 4999 then
lm <= (others => '0');fpa<= not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(inclk)
begin
if(inclk'event and inclk ='1')then
if sina="0000"then
ssouta<=souta; souta<="0000";
ssoutb<=soutb; soutb<="0000";
sina<=ina;
else
sina<=sina-1;
if souta=9 then
souta<="0000";
if soutb=9 then
soutb<="0000";
else
soutb<=soutb+1;
end if;
else
souta<=souta+1;
end if;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if st=2 then
st<=(others=>'0');
else
st<=st+1;
end if;
end if;
end process;
process(st)
begin
case st is
when"00"=>
outseg<=outa;
outbit<="10";
when"01"=>
outseg<=outb;
outbit<="01";
when others=>
outbit<="11";
end case;
end process;
with ssouta select
outa <=
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111",
"11111100" when others;
with ssoutb select
outb <=
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111",
"11111100" when others;
end arch_bcdconvert4;
14. Complete corresponding functions as required .
Use text input method to design a 8 position BCD Code conversion circuit , Download and test , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bcdconvert8 is
port(ina:in std_logic_vector(7 downto 0);
inclk:in std_logic;
outseg: out std_logic_vector(7 downto 0);
outbit: out std_logic_vector(2 downto 0));
end bcdconvert8;
architecture arch_bcdconvert8 of bcdconvert8 is
signal sina:std_logic_vector(7 downto 0);
signal souta,soutb,soutc:std_logic_vector(3 downto 0);
signal ssouta,ssoutb,ssoutc:std_logic_vector(3 downto 0);
signal outa,outc,outb:std_logic_vector(7 downto 0);
signal lm:std_logic_vector(12 downto 0);
signal fpa:std_logic;
signal st:std_logic_vector(1 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk ='1')then
if lm = 4999 then
lm <= (others => '0');fpa<= not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(inclk)
begin
if(inclk'event and inclk ='1')then
if sina="00000000"then
ssouta<=souta; souta<="0000";
ssoutb<=soutb; soutb<="0000";
sina<=ina;
else
sina<=sina-1;
if souta=9 then
souta<="0000";
if soutb=9 then
soutb<="0000";
else
soutb<=soutb+1;
end if;
else
souta<=souta+1;
end if;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if st=2 then
st<=(others=>'0');
else
st<=st+1;
end if;
end if;
end process;
process(st)
begin
case st is
when"00"=>
outseg<=outa;
outbit<="110";
when"01"=>
outseg<=outb;
outbit<="101";
when"10"=>
outseg<=outc;
outbit<="011";
when others=>
outbit<="111";
end case;
end process;
with ssouta select
outa <=
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111",
"11111100" when others;
with ssoutb select
outb <=
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111",
"11111100" when others;
with ssoutc select
outc <=
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111",
"11111100" when others;
end arch_bcdconvert8;
15. Complete corresponding functions as required .
Use text input method to design a 9 position BCD Code conversion circuit , Download and test , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test is
port(ina :in std_logic_vector(8 downto 0);
inclk:in std_logic;
outseg:out std_logic_vector(7 downto 0);
outbit:out std_logic_vector(2 downto 0));
end test;
architecture arth_bcdconvert of test is
signal sina:std_logic_vector(8 downto 0);
signal souta,soutb,soutc:std_logic_vector(3 downto 0);
signal ssouta,ssoutb,ssoutc:std_logic_vector(3 downto 0);
signal outa,outb,outc:std_logic_vector(7 downto 0);
signal lm:std_logic_vector(12 downto 0);
signal fpa:std_logic;
signal st:std_logic_vector(1 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk = '1')then
if lm = 2499 then
lm<=(others=>'0');fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(inclk)
begin
if(inclk'event and inclk = '1')then
if sina = "00000000"then
ssouta<=souta;
souta<="0000";
ssoutb <=soutb;
soutb<="0000";
ssoutc<=soutc;
soutc<="0000";
sina<=ina;
else
sina<=sina-1;
if souta = 9 then
souta<="0000";
if soutb = 9 then
soutb<="0000";
soutc<=soutc+1;
else
soutb <=soutb +1;
end if;
else
souta <=souta+1;
end if;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa = '1')then
if st=2 then
st<=(others=>'0');
else
st<= st+1;
end if;
end if;
end process;
process(st)
begin
case st is
when "00"=>
outseg<=outa;
outbit<="110";
when "01"=>
outseg<=outb;
outbit<="101";
when "10"=>
outseg<=outc;
outbit<="011";
when others=>
outbit<="111";
end case;
end process;
WITH ssouta SELECT
outa <=
"01100000"WHEN"0001", --1
"11011010"WHEN"0010", --2
"11110010"WHEN"0011", --3
"01100110"WHEN"0100", --4
"10110110"WHEN"0101", --5
"10111110"WHEN"0110", --6
"11100000"WHEN"0111", --7
"11111110"WHEN"1000", --8
"11110110"WHEN"1001", --9
"11101110"WHEN"1010", --A
"00111110"WHEN"1011", --b
"10011100"WHEN"1100", --C
"01111010"WHEN"1101", --d
"10011110"WHEN"1110", --E
"10001110"WHEN"1111", --F
"11111100"WHEN OTHERS; --0
WITH ssoutb SELECT
outb <=
"01100000"WHEN"0001", --1
"11011010"WHEN"0010",--2
"11110010"WHEN"0011", --3
"01100110"WHEN"0100", --4
"10110110"WHEN"0101", --5
"10111110"WHEN"0110", --6
"11100000"WHEN"0111", --7
"11111110"WHEN"1000", --8
"11110110"WHEN"1001", --9
"11101110"WHEN"1010", --A
"00111110"WHEN"1011", --b
"10011100"WHEN"1100", --C
"01111010"WHEN"1101", --d
"10011110"WHEN"1110", --E
"10001110"WHEN"1111", --F
"11111100"WHEN OTHERS; --0
WITH ssoutc SELECT
outc <=
"01100000"WHEN"0001", --1
"11011010"WHEN"0010",--2
"11110010"WHEN"0011", --3
"01100110"WHEN"0100", --4
"10110110"WHEN"0101", --5
"10111110"WHEN"0110", --6
"11100000"WHEN"0111", --7
"11111110"WHEN"1000", --8
"11110110"WHEN"1001", --9
"11101110"WHEN"1010", --A
"00111110"WHEN"1011", --b
"10011100"WHEN"1100", --C
"01111010"WHEN"1101", --d
"10011110"WHEN"1110", --E
"10001110"WHEN"1111", --F
"11111100"WHEN OTHERS; --0
end arth_bcdconvert;
16. Complete corresponding functions as required .
Use text input method to design a 4×4 Keyboard scanning and display circuit , And carry out functional test , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(1 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(1 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(5 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =59999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="01"then
if inkeymap/="11"then
keyout<=chuout&inkeymap;
end if;
chuout<="10";
elsif chuout="10"then
if inkeymap/="11"then
keyout<=chuout & inkeymap;
end if;
chuout<="01";
else
chuout<="01";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "0111"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"3f";
when"10"=> outled <=x"06";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"66";
when"10"=> outled <=x"6d";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"7f";
when"10"=> outled <=x"67";
when others=> outled <=x"00";
end case;
when "1110"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"39";
when"10"=> outled <=x"5e";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
17. Complete corresponding functions as required .
Use text input method to design a 4×4 Keyboard scanning and display circuit , Requires top-down 、 From left to right “0-
F” , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(3 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(3 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(7 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =109999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="1110"then
if inkeymap/="1111"then
keyout<=chuout&inkeymap;
end if;
chuout<="1101";
elsif chuout="1101"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1011";
elsif chuout="1011"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="0111";
elsif chuout="0111"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1110";
else
chuout<="1110";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "0111"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"3f";
when"1011"=> outled <=x"06";
when"1101"=> outled <=x"5b";
when"1110"=> outled <=x"4f";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"66";
when"1011"=> outled <=x"6d";
when"1101"=> outled <=x"7d";
when"1110"=> outled <=x"07";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"7f";
when"1011"=> outled <=x"67";
when"1101"=> outled <=x"77";
when"1110"=> outled <=x"7c";
when others=> outled <=x"00";
end case;
when "1110"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"39";
when"1011"=> outled <=x"5e";
when"1101"=> outled <=x"79";
when"1110"=> outled <=x"71";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
18. Complete corresponding functions as required .
Use text input method to design a 4×4 Keyboard scanning and display circuit , Requires top-down 、 From right to left, there are “0- F” , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(3 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(3 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(7 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =109999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="1110"then
if inkeymap/="1111"then
keyout<=chuout&inkeymap;
end if;
chuout<="1101";
elsif chuout="1101"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1011";
elsif chuout="1011"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="0111";
elsif chuout="0111"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1110";
else
chuout<="1110";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "0111"=> -- From top to bottom
case keyout(7 downto 4)is
when"1110"=> outled <=x"3f"; -- From right to left
when"1101"=> outled <=x"06";
when"1011"=> outled <=x"5b";
when"0111"=> outled <=x"4f";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"66";
when"1101"=> outled <=x"6d";
when"1011"=> outled <=x"7d";
when"0111"=> outled <=x"07";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"7f";
when"1101"=> outled <=x"67";
when"1011"=> outled <=x"77";
when"0111"=> outled <=x"7c";
when others=> outled <=x"00";
end case;
when "1110"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"39";
when"1101"=> outled <=x"5e";
when"1011"=> outled <=x"79";
when"0111"=> outled <=x"71";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
19. Use text input method to design a 4×4 Keyboard scanning and display circuit , Requires bottom-up 、 From left to right “0-
F” , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(3 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(3 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(7 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =109999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="1110"then
if inkeymap/="1111"then
keyout<=chuout&inkeymap;
end if;
chuout<="1101";
elsif chuout="1101"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1011";
elsif chuout="1011"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="0111";
elsif chuout="0111"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1110";
else
chuout<="1110";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "1110"=> -- Bottom up
case keyout(7 downto 4)is
when"0111"=> outled <=x"3f"; -- From left to right
when"1011"=> outled <=x"06";
when"1101"=> outled <=x"5b";
when"1110"=> outled <=x"4f";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"66";
when"1011"=> outled <=x"6d";
when"1101"=> outled <=x"7d";
when"1110"=> outled <=x"07";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"7f";
when"1011"=> outled <=x"67";
when"1101"=> outled <=x"77";
when"1110"=> outled <=x"7c";
when others=> outled <=x"00";
end case;
when "0111"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"39";
when"1011"=> outled <=x"5e";
when"1101"=> outled <=x"79";
when"1110"=> outled <=x"71";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
20. Complete corresponding functions as required .
Use text input method to design a 4×4 Keyboard scanning and display circuit , Requires bottom-up 、 From right to left, there are “0-
F” , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(3 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(3 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(7 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =109999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="1110"then
if inkeymap/="1111"then
keyout<=chuout&inkeymap;
end if;
chuout<="1101";
elsif chuout="1101"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1011";
elsif chuout="1011"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="0111";
elsif chuout="0111"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1110";
else
chuout<="1110";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "1110"=> -- Bottom up
case keyout(7 downto 4)is
when"1110"=> outled <=x"3f"; -- From right to left
when"1101"=> outled <=x"06";
when"1011"=> outled <=x"5b";
when"0111"=> outled <=x"4f";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"66";
when"1101"=> outled <=x"6d";
when"1011"=> outled <=x"7d";
when"0111"=> outled <=x"07";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"7f";
when"1101"=> outled <=x"67";
when"1011"=> outled <=x"77";
when"0111"=> outled <=x"7c";
when others=> outled <=x"00";
end case;
when "0111"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"39";
when"1101"=> outled <=x"5e";
when"1011"=> outled <=x"79";
when"0111"=> outled <=x"71";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
21. Complete corresponding functions as required .
Use text input method to design a 2（ Scan code ）×4（ Return code ） Keyboard scanning and display circuit , And carry out functional test , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(1 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(1 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(5 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =59999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="01"then
if inkeymap/="11"then
keyout<=chuout&inkeymap;
end if;
chuout<="10";
elsif chuout="10"then
if inkeymap/="11"then
keyout<=chuout & inkeymap;
end if;
chuout<="01";
else
chuout<="01";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "0111"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"3f";
when"10"=> outled <=x"06";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"66";
when"10"=> outled <=x"6d";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"7f";
when"10"=> outled <=x"67";
when others=> outled <=x"00";
end case;
when "1110"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"39";
when"10"=> outled <=x"5e";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
22. Complete corresponding functions as required .
Use text input method to design a 4（ Scan code ）×2（ Return code ） Keyboard scanning and display circuit , And carry out functional test , Record test results .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(1 downto 0);
outkey: out std_logic_vector(3 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(1 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(1 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(3 downto 0);
signal inkeymap :std_logic_vector(1 downto 0);
signal keyout :std_logic_vector(5 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =59999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="1110"then
if inkeymap/="1111"then
keyout<=chuout&inkeymap;
end if;
chuout<="1101";
elsif chuout="1101"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1011";
elsif chuout="1011"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="0111";
elsif chuout="0111"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1110";
else
chuout<="1110";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(1 downto 0)is
when "01"=>
case keyout(5 downto 2)is
when"0111"=> outled <=x"3f";
when"1011"=> outled <=x"06";
when"1101"=> outled <=x"5b";
when"1110"=> outled <=x"4f";
when others=> outled <=x"00";
end case;
when "10"=>
case keyout(5 downto 2)is
when"0111"=> outled <=x"66";
when"1011"=> outled <=x"6d";
when"1101"=> outled <=x"7d";
when"1110"=> outled <=x"07";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
23. Complete corresponding functions as required .
Using text input method to design a traffic light program , The red light on the main road is on 30 second , The green light is on 25 second , The two lights are separated by yellow lights
Intermittent flicker 5 second , And use the digital tube to display the countdown , Record the experimental phenomena .
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CROSS IS PORT
(INCLK: IN STD_LOGIC;
LED_R_Z:OUT STD_LOGIC;
LED_G_Z:OUT STD_LOGIC;
LED_R_F:OUT STD_LOGIC;
LED_G_F:OUT STD_LOGIC;
outseg: out std_logic_vector(7 downto 0);
outbit: out std_logic_vector(1 downto 0));
END CROSS;
ARCHITECTURE A_CROSS OF CROSS IS
COMPONENT bcdconvert
PORT(ina:in std_logic_vector(7 downto 0);
inclk:in std_logic;
outseg: out std_logic_vector(7 downto 0);
outbit: out std_logic_vector(1 downto 0));
END COMPONENT;
SIGNAL FP:STD_LOGIC_VECTOR(24 DOWNTO 0);
SIGNAL FPA:STD_LOGIC;
SIGNAL CNT:STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE LED_STATE IS (S0,S1,S2,S3);
SIGNAL CS:LED_STATE;
BEGIN
U1:bcdconvert PORT MAP(CNT,INCLK,OUTSEG,OUTBIT);
PROCESS(INCLK)
BEGIN
IF(INCLK'EVENT AND INCLK='1')THEN
IF FP=24999999 THEN
FP<=(OTHERS=>'0');
FPA<=NOT FPA;
ELSE FP<=FP+1;
END IF;
END IF;
END PROCESS;
PROCESS(FPA)
BEGIN
IF RISING_EDGE(FPA)THEN
CASE CS IS
WHEN S0=>
IF CNT=0 THEN -- If the count value is 0
CNT<=X"07"; --00001001, That is to say 10 It's binary 5
CS<=S1; -- Get into S1 state
ELSE CNT<=CNT-1;
CS<=S0; -- If the count is not over , Keep going back S0 Count
END IF;
WHEN S1=>
IF CNT=0 THEN -- If the count value is 0
CNT<=X"3B"; --00111011, That is to say 10 It's binary 59
CS<=S2; -- Get into S2 state
ELSE CNT<=CNT-1;
CS<=S1; -- If the count is not over , Keep going back S1 Count
END IF;
WHEN S2=>
IF CNT=0 THEN
CNT<=X"07";
CS<=S3;
ELSE CNT<=CNT-1;
CS<=S2;
END IF;
WHEN S3=>
IF CNT=0 THEN
CNT<=X"3B";
CS<=S0;
ELSE CNT<=CNT-1;
CS<=S3;
END IF;
WHEN OTHERS=>
CNT<=(OTHERS=>'0');
CS<=S0;
END CASE;
END IF;
END PROCESS;
LED_R_Z<='0'WHEN CS=S0 ELSE -- The main road is red
'0' WHEN(CS=S1 OR CS=S3) AND FPA='1' ELSE
'1';
LED_G_Z<='0'WHEN CS=S2 ELSE -- The main road is green
'0' WHEN(CS=S1 OR CS=S3) AND FPA='1' ELSE
'1';
LED_R_F<='0'WHEN CS=S2 ELSE -- Side Rd
'0' WHEN(CS=S1 OR CS=S3) AND FPA='1' ELSE
'1';
LED_G_F<='0'WHEN CS=S0 ELSE
'0' WHEN(CS=S1 OR CS=S3) AND FPA='1' ELSE
'1';
END A_CROSS;
24. Complete corresponding functions as required .
Using text input method to design a traffic light program , The red light on the main road is on 59 second , The green light is on 59 second , The two lights are separated by yellow lights
Intermittent flicker 7 second , And use the digital tube to display the countdown , Record the experimental phenomena .
IF CNT=0 THEN -- If the count value is 0
CNT<=X"06"; -- CS<=S1; -- Get into S1 state
ELSE CNT<=CNT-1;
CS<=S0; -- If the count is not over , Keep going back S0 Count
END IF;
WHEN S1=>
IF CNT=0 THEN -- If the count value is 0
CNT<=X"3a"; -- CS<=S2; -- Get into S2 state
ELSE CNT<=CNT-1;
CS<=S1; -- If the count is not over , Keep going back S1 Count
END IF;
WHEN S2=>
IF CNT=0 THEN
CNT<=X"06";
CS<=S3;
ELSE CNT<=CNT-1;
CS<=S2;
END IF;
WHEN S3=>
IF CNT=0 THEN
CNT<=X"3a";
CS<=S0;
ELSE CNT<=CNT-1;
CS<=S3;
END IF;
WHEN OTHERS=>
CNT<=(OTHERS=>'0');
CS<=S0;
END CASE;
END IF;
END PROCESS;
25. Using text input method to design a traffic light program , The red light on the main road is on 10 second , The green light is on 27 second , The two lights are separated by yellow lights
Intermittent flicker 8 second , And use the digital tube to display the countdown , Record the experimental phenomena .
IF CNT=0 THEN -- If the count value is 0
CNT<=X"07"; --
CS<=S1; -- Get into S1 state
ELSE CNT<=CNT-1;
CS<=S0; -- If the count is not over , Keep going back S0 Count
END IF;
WHEN S1=>
IF CNT=0 THEN -- If the count value is 0
CNT<=X"1a"; -- CS<=S2; -- Get into S2 state
ELSE CNT<=CNT-1;
CS<=S1; -- If the count is not over , Keep going back S1 Count
END IF;
WHEN S2=>
IF CNT=0 THEN
CNT<=X"07";
CS<=S3;
ELSE CNT<=CNT-1;
CS<=S2;
END IF;
WHEN S3=>
IF CNT=0 THEN
CNT<=X"09";
CS<=S0;
ELSE CNT<=CNT-1;
CS<=S3;
END IF;
WHEN OTHERS=>
CNT<=(OTHERS=>'0');
CS<=S0;
END CASE;
END IF;
END PROCESS;
26. Complete corresponding functions as required .
Using text input method to design a traffic light program , The red light on the main road is on 40 second , The green light is on 45 second , The two lights are separated by yellow lights
Intermittent flicker 5 second , And use the digital tube to display the countdown , Record the experimental phenomena .
IF RISING_EDGE(FPA)THEN
CASE CS IS
WHEN S0=>
IF CNT=0 THEN -- If the count value is 0
CNT<=X"04"; – CS<=S1; -- Get into S1 state
ELSE CNT<=CNT-1;
CS<=S0; -- If the count is not over , Keep going back S0 Count
END IF;
WHEN S1=>
IF CNT=0 THEN -- If the count value is 0
CNT<=X"2c"; –
CS<=S2; -- Get into S2 state
ELSE CNT<=CNT-1;
CS<=S1; -- If the count is not over , Keep going back S1 Count
END IF;
WHEN S2=>
IF CNT=0 THEN
CNT<=X"04";
CS<=S3;
ELSE CNT<=CNT-1;
CS<=S2;
END IF;
WHEN S3=>
IF CNT=0 THEN
CNT<=X"27";
CS<=S0;
ELSE CNT<=CNT-1;
CS<=S3;
END IF;
WHEN OTHERS=>
CNT<=(OTHERS=>‘0’);
CS<=S0;
END CASE;
END IF;
END PROCESS;
27. Simulation verification
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(CLK,RST,EN,LOAD:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END ENTITY CNT10;
ARCHITECTURE BHV OF CNT10 IS
BEGIN
PROCESS(CLK,RST,EN,LOAD)
VARIABLE Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RST='0'THEN
Q:=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1'THEN
IF EN='1'THEN
IF(LOAD='0')THEN
Q:= DATA;
ELSE
IF Q < 9 THEN
Q:=Q+1;
ELSE Q:=(OTHERS=>'0');
END IF;
END IF;
END IF;
END IF;
IF Q="1001"THEN
COUT<='1';
ELSE COUT<='0';
END IF;
DOUT<=Q;
END PROCESS;
END ARCHITECTURE BHV;
incentive ：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TEST IS END TEST;
ARCHITECTURE behaviour OF TEST IS
COMPONENT CNT10
PORT(CLK:IN STD_LOGIC;
RST:IN STD_LOGIC;
EN:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END COMPONENT;
SIGNAL CLK:STD_LOGIC:='0';
SIGNAL RST:STD_LOGIC:='1';
SIGNAL EN:STD_LOGIC:='0';
SIGNAL LOAD:STD_LOGIC:='1';
SIGNAL DATA:STD_LOGIC_VECTOR(3 DOWNTO 0):=(OTHERS=>'0');
SIGNAL DOUT:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUT:STD_LOGIC;
CONSTANT CLK_PERIOD:TIME:=50 ns;
BEGIN
UUT:CNT10 PORT MAP(CLK=>CLK,
RST=>RST,
EN=>EN,
LOAD=>LOAD,
DATA=>DATA,
DOUT=>DOUT,
COUT=>COUT);
CLK_PROCESS:PROCESS
BEGIN
CLK<='0';
WAIT FOR CLK_PERIOD/2;
CLK<='1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
PROCESS
BEGIN
RST<='1';
WAIT FOR 110 NS;
RST<='0';
WAIT FOR 110 NS;
RST<='1';
WAIT;
END PROCESS;
EN<='0','1'AFTER 40 NS;
LOAD<='1','0'AFTER 910 NS,'1'AFTER 940 NS;
DATA<="0100","0110" AFTER 400 NS,"0111" AFTER 700 NS,"0100" AFTER 1000 NS;
END;
28. incentive ：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TEST IS
END TEST;
ARCHITECTURE BCHAVIOR OF TEST IS
COMPONENT DFF1
port(clk,d: in std_logic;
q:out std_logic);
END COMPONENT;
SIGNAL CLK: STD_LOGIC:='0';
SIGNAL d:STD_LOGIC:='0';
signal q:std_LOGIC;
CONSTANT CLK_PERIOD:TIME:=50 ns;
BEGIN
UUT:DFF1 PORT MAP(CLK=>CLK,
d=>d,
q=>q);
CLK_PROCESS:PROCESS
BEGIN
CLK<='0';
WAIT FOR CLK_PERIOD/2;
CLK<='1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
d<='0','1' after 30 ns,'0' after 60 ns,'1' after 72 ns,
'0' after 80 ns,'1' after 140 ns,'0' after 180 ns;
END BCHAVIOR;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp IS
PORT(clk_in:in std_logic;
clk_1k:out std_logic);
END ENTITY fp;
ARCHITECTURE BHV OF fp IS
signal cnt_1k:integer range 0 to 24999;
BEGIN
PROCESS(clk_in)
BEGIN
IF (clk_in'event and clk_in='1')then
if cnt_1k=24999 then
cnt_1k<=0;
else
cnt_1k<=cnt_1k+1;
END IF;
END IF;
end process;
process(clk_in)
begin
if (clk_in'event and clk_in='1')then
if cnt_1k>12499 then
clk_1k<='1';
else
clk_1k<='0';
end if;
end if;
END PROCESS;
END ARCHITECTURE BHV;
incentive ：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TEST IS
END TEST;
ARCHITECTURE BCHAVIOR OF TEST IS
COMPONENT fp
port(clk_in: in std_logic;
clk_1k:out std_logic);
END COMPONENT;
SIGNAL clk_in: STD_LOGIC:='0';
signal clk_1k: STD_LOGIC:='0';
CONSTANT CLK_PERIOD:TIME:=40 ns;
BEGIN
UUT:fp PORT MAP(clk_in=>clk_in,
clk_1k=>clk_1k);
CLK_PROCESS:PROCESS
BEGIN
clk_in<='0';
WAIT FOR CLK_PERIOD/2;
clk_in<='1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
END BCHAVIOR;
.vhd Script , Engineering accessories :
Complete project file download link
边栏推荐
- The most complete preview! Huawei cloud wonderful agenda collection
- CS for mobile security [nethunter]
- Start blogging
- Enterprise wechat H5_ Authentication, H5 application web page authorization login to obtain identity
- 【Matlab】二维曲线
- Leaflet that supports canvas Path. Dashflow dynamic flow direction line
- Accelerating with Dali modules
- Tableau
- M_ 8: Design a MySQL table for message queue to store message data
- Leetcode 2200. Find all k nearest neighbor subscripts in the array (yes, one pass)
猜你喜欢
一篇文章学会子网划分
PLC也能制作小游戏----Codesys编写猜数字小游戏
PMP renewal | PDU specific operation diagram
Enterprise wechat H5_ Authentication, H5 application web page authorization login to obtain identity
Introduction to message oriented middleware (message queue)
The PMP examination time in March 2022 is set -- "March 27"
2022 electrician (elementary) operation certificate examination question bank and online simulation examination
【HCIE论述】STP-A
array
CV—BaseLine总结（从AlexNet到SENet的发展历程）
随机推荐
Summary of the lowest level error types in PHP
Vscode实现PHP在浏览器实时预览
H5时代leaflet中还在用DivIcon？
The PMP examination time in March 2022 is set -- "March 27"
Will PM (Project Manager) take the PMP Exam?
June 11, 2022 diary: Mr. Wang's spring, mixed in
Tableau
[matlab] two dimensional curve
如何让矢量瓦片配图神器maputnik支持 geoserver
Develop a web office suite from scratch (5): mouse hover over text
【Matlab】基础运算
Is the PMP training organization an actual training?
Video tracker error troubleshooting
The most complete preview! Huawei cloud wonderful agenda collection
Introduction to message oriented middleware (message queue)
最全预告！华为云精彩议程火速收藏
[leetcode] understanding and usage of map[key]+
How to get Matplotlib figure size
So, what is the difference between e.target and e.currenttarget?
Leetcode 2200. 找出数组中的所有 K 近邻下标(可以,一次过)