Chapter 9 practical modeling technology

Preface

• Here it is... Here it is ,Verilog Other enhancements to the language , These characteristics make Verilog Language has more flexibility in modeling and design analysis .

Processes are continuously assigned values

• Process assignment ： Assign a value to a register , Values are always stored in registers , Until another process assignment stores another value in this register .
• Processes are continuously assigned values ： It is allowed to add the value of the expression continuously in a limited period of time （ drive ） To register or wire network . Rewrite the existing value of a register or line .

assign and deassign

• keyword ：assign、 deassign
• It is used to represent the continuous assignment statement of the first kind of procedure , Not recommended , Get to know .
  

force and release

• keyword ：force 、release
• The second form of procedure continuous assignment statement , It can be used to rewrite （ Cover ） Assignment on register , You can also rewrite （ Cover ） Assignment on the wire network .
• Typical applications ： During interactive debugging .
• It is not recommended to use it inside the design module , Should only appear in incentives , Or just as a debug statement .

Act on registers

• Rewrite within a controlled period q and qbar Value .
  

Function online

• After the wire net is released , Immediately return to your normal drive . The network can be forcibly assigned an expression or a value .
  

Rewrite parameters

• Also known as coverage parameter . Parameters can be defined within the module definition , But in Verilog During module compilation , Parameter values can be changed individually for each module call .
• The two methods ： adopt defparam sentence 、 Parameter assignment through module call .

defparam sentence

• keyword ：defparam
• Parameter values can be changed in any module call , The hierarchical name of the module call can be used to rewrite （ Cover ） In the statement of parameter value .
  
• There can be more than one in a module defparam sentence .
• It can be used defparam Statement overrides any parameter .
• ok, Another bad link ,defparam Statements are considered bad code style , It is suggested that Verilog HDL Use alternative forms in code . Just get to know .

Parameter values of module instances

• When calling a module, you can rewrite （ Cover ） Its originally defined parameter value .
• Modify the above example as follows
• Parameters are assigned by name
  

Conditional compilation and execution

• Conditional compilation ：Verilog Part of the code may be used in a compilation environment , But it doesn't apply to another environment . The designer specifies in the code that a part of the code can be compiled only after setting a specific flag . This is conditional compilation .
• Condition execution ： Empathy , When the program runs , Only after a certain flag is set can it be executed Verilog Some parts of the design .

Conditional compilation

• Compile instructions ：

  `ifdef, `ifndef, `else, `elsif, `endif
  

• as follows
  

• Because the symbol in front of the instruction conflicts with the editor , The following description without symbols .

• ifdef and ifndef Instructions can appear anywhere in the design .

• else Instructions are optional . One else The instruction can match at most one ifdef perhaps ifndef.

• One ifdef perhaps ifndef Can match any number of elsif command .

• ifdef perhaps ifndef Always use the corresponding endif To the end .

• stay Verilog In file , The conditional compilation flag can be used define Statement settings .

Condition execution

• The conditional execution flag allows the designer to control the flow of statement execution at run time . All statements are compiled , But execute them conditionally .
• The conditional execution flag can only be used for behavior statements .
• keyword ：$test$plusargs$、$value$plusargs$
• use $test$plusargs$ control
  
• use $value$plusargs$ Further control condition execution , This system task is used to test the parameter value of the call option , If no matching call options are found , be $value$plusargs$ return 0, If you find it , be $value$plusargs$ Return non 0 value .
  

Time scale

• In the simulation , The delay value of a module needs to be defined in a certain time unit .

• keyword ：'timescale

• Such as 'timescale 1ns/1ps among ,1ns Is the unit of measurement of the specified time and delay ,1ps Is the precision of rounding the delay value .

• Only 1,10 and 100 Is the legal integer that describes the time unit and time accuracy .

  `timescale 100ns/1ns
  module fx();
  ...
  // 500ns clk Flip once 
  #5 clk = ~clk;
  ...
  

Common system tasks

• Common system tasks ： File output 、 Display hierarchy 、 Strobe display 、 Random number generation 、 Memory initialization 、 Value change dump, etc .

File output

• Verilog The results are usually output to standard output and files verilog.log in , You can redirect its output to the selected file .

Open file

• System tasks ：$fopen

• usage ：

  • One ,$fopen(" file name ");
  • Two ,file_handle = $fopen(" file name ");

• $fopen Return to one 32 Bit multichannel descriptor , And only one bit of the multi-channel descriptor is set to 1.

• The standard output has a multi-channel descriptor , Its lowest position （ The first 0 position ） Is set to 1.

• Standard output is also called channel 0, Always open . $fopen Each call of will open a new channel , And will return a 32 Channel character of bit , You can set the 1 position , Second …… Until 30 position , The first 31 Bit is reserved bit .

• Advantages of multichannel ： You can choose to write multiple files at the same time .

  //  Multichannel descriptor 
  integer handle1, handle2;
  
  //  Standard output is on , That is to say 0 Location 1
  // descriptor = 32'h0000_0001
  
  initial
  begin
  	handle1 = $fopen("file1.out");	// handle1 = 32'h0000_0002( The first 1 Location 1)
  	handle2 = $fopen("file1.out");	// handle2 = 32'h0000_0004( The first 2 Location 1)
  end
  

Writing documents

• System tasks ：$fdisplay、$fmonitor、$fwrite、$fstrobe
• Commonly used $fdisplay、$fmonitor
• usage ：
  • $fdisplay(<file_descriptor>,p1,p2,...,pn);
  • $fmonitor(<file_descriptor>,p1,p2,...,pn);
  • p1,p2,...,pn It could be a variable 、 Signal name or quoted string .
• The file descriptor is a multichannel descriptor , It can be a file handle or a bitwise combination of multiple file handles .
• Verilog The output will be written to the file descriptor with a value of 1 All files associated with the phase of .
  

Close file

• System tasks ：$fclose
• usage ：$fclose(<file_descriptor>);

Display hierarchy

• Use any display task ,$display,$write,$monitor,$strobe In the task %m Options , Show any level of hierarchy .
  
• Output results
  

Strobe display

• System tasks ：$strobe
• $strobe Provide synchronization mechanism , It can ensure that all other statements assigned along the same clock edge will display data after execution .
  
• The value of the rising edge of the clock is in the statement a=b and c=d After execution, it will display .

Random number generation

• System tasks ：$random
• usage ：
  • $random;
  • $random(<seed>);
  • <seed> It's optional , Used to ensure that the same sequence of random numbers is generated each time the test is run , The value could be reg,integer perhaps time Variable .
• Mission $random Return to one 32 An integer .
  
• Generate signed integer
  

Initialization memory

• Initialize the memory according to the data file .
• System tasks ：$readmemb（ Binary number ）、$readmemh（ Hexadecimal number ）
• usage ：
  • $readmemb("<file_name>", <memory_name>);
  • $readmemb("<file_name>", <memory_name>, <start_addr>);
  • $readmemb("<file_name>", <memory_name>, <start_addr>, <finish_addr>);
  • $readmemh Same as .
  • File name and memory name are required ,<start_addr> and <finish_addr> It's optional .
• Here's an example
  
• file init.dat Contains initialization data . The address is expressed in hexadecimal numbers , The data is separated by a space character , The data can contain x or z.
  
• Simulation test results
  

Value change dump file

• Value change dump file （VCD） What is it? ？
• One ASCⅡ file , Including simulation time 、 The definition of range and signal and the change of signal value during simulation operation .
• How to use it ？
• All signals in the design or selected signal sets can be written in the simulation process VCD file , The post-processing tool can put VCD File as input and put the hierarchy information 、 The signal value and signal waveform are displayed .
  
• System tasks include ：
  • $dumpvars： Select the module instance or module instance signal to dump ;
  • $dumpfile： choice VCD The name of the document ;
  • $dumpon： Select the starting point of the dump ;
  • $dumpoff： Select the destination of the dump ;
  • $dumpall： Select generate test points ;
• As shown in the following example