STM32 watchdog study

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Definition of cute dog

Single chip microcomputer system in the external interference will appear under the phenomenon of program running, leading to the emergence of dead cycle , The watchdog circuit is to avoid this . The role of a watchdog is to （ Through the timer counter ） No dog feed signal received （ Express MCU It's gone ）, The processor can reset and restart automatically （ Send a reset signal ）.

STM32 The watchdog

STM32 The chip has two watchdog , One is Independent watchdog （IWDG）, The other is Form watchdog （WWDG）

• First, let's talk about the independent watchdog ： STM32 The independent watchdog consists of an internal specialized 40Khz Low speed clock drive , Even if the master clock fails , It still works . It should be noted here that the clock of the independent watchdog is an internal RC The clock , So it's not accurate 40Khz, But in 30~60Khz A variable clock between , It's just that when we estimate , With 40Khz To calculate the frequency of , The watchdog is not very precise about time , therefore , The clock is a little off , All are acceptable .
• The independent watchdog has a free running decrement counter
• The independent watchdog clock consists of an independent RC The oscillator provides ( It can work in stop and standby modes )
• When the independent watchdog is activated , Then the counter counts to 0x000 A reset occurs when the system is running

Configuration working code of independent watchdog ：

 1 void IWDG_Init(u8 prer,u16 rlr)
 2 {
 3　　  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); //① Enable on register  I  Write operations 
 4 　　 IWDG_SetPrescaler(prer); //② Set up  IWDG  Prescaled value : Set up  IWDG  Prescaled value 
 5 　　 IWDG_SetReload(rlr); //② Set up  IWDG  Reload value , Pay attention not to be greater than 0xfff
 6  　　IWDG_ReloadCounter(); //③ according to  IWDG  Reload the value of the load register  IWDG  Counter 
 7  　　IWDG_Enable(); //④ Can make  IWDG
 8 }
 9 // Hello, the independent watchdog 
10 void IWDG_Feed(void)
11 {
12　　  IWDG_ReloadCounter();//reload
13 }

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Main logical area code ：

 1 delay_init();// Delay function initialization 
 2 NVIC_Configuration(); // Set up  NVIC  Interrupt grouping  2:2  Bit preemption priority ,2  Bit response priority 
 3 KEY_Init(); // Key initialization 
 4 IWDG_Init(4,625); // And the frequency division number is  64, The overload value is  625, The overflow time is  1s
 5 while(1)
 6 {
 7     if(KEY_Scan(0)==KEY_UP)
 8     {
 9         IWDG_Feed(); // If   Press the key , Then feed the dog 
10     }
11     delay_ms(10);
12 }

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• Look at the window watchdog Window watchdog （WWDG） It is usually used to monitor the software failure caused by external interference or unforeseen logical conditions . Unless the value of the down counter is in T6 position （WWDG->CR No. 6 of ） become 0 Previously refreshed , When the watchdog circuit reaches the preset time cycle , Will produce a MCU Reset . When the down counter reaches the window configuration register (WWDG->CFR) Before the number , If 7 Bit down counter value ( In the control register ) Has been refreshed , Then there will also be a MCU Reset . This indicates that the down counter needs to be refreshed in a limited time window .
• Condition reset ─ When the value of the down counter is less than 0x40,( If the watchdog is activated ) Reset is generated . ─ When the decrement counter is reloaded outside the window ,( If the watchdog is activated ) Reset is generated .

If the watchdog is activated and interrupt is allowed , When the decrement counter equals 0x40 An early wake-up interrupt is generated (EWI), It can be used to reload counters to avoid WWDG Reset

 The formula for calculating watchdog time ：

 The window watchdog timeout formula is as follows ：

Twwdg=(4096×2^WDGTB×(T[5:0]+1)) /Fpclk1;

 among ：

Twwdg：WWDG  Timeout time （ Unit is  ms）

Fpclk1：APB1  The clock frequency of （ Unit is  Khz）

WDGTB：WWDG  The prescaler coefficient of 

T[5:0]： The watchdog's counter is low  6  position 

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Window watchdog configuration work code ：

 1 void WWDG_Init(u8 tr,u8 wr,u32 fprer)
 2 {
 3 　　　　RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE); // WWDG  Clock enable 
 4　　　　 WWDG_CNT=tr&WWDG_CNT; // initialization  WWDG_CNT.
 5 　　　　WWDG_SetPrescaler(fprer); // Set up  IWDG  Prescaled value 
 6 　　　　WWDG_SetWindowValue(wr); // Set window values 
 7　　　　 WWDG_Enable(WWDG_CNT);
 8 　　　　// To enable a watchdog , Set up  counter
 9 　　　　WWDG_ClearFlag(); // Clear the early wake-up interrupt flag bit 
10　　　　 WWDG_NVIC_Init(); // Initialize the window watchdog  NVIC
11　　　　 WWDG_EnableIT(); // Open window watchdog interrupt 
12 }
13 // Heavy set  WWDG  The value of the counter 
14 void WWDG_Set_Counter(u8 cnt)
15 {
16 　　　　WWDG_Enable(cnt); // To enable a watchdog , Set up  counter .
17 }
18 // Window watchdog interrupt service program 
19 void WWDG_NVIC_Init()
20 {
21　　　　 NVIC_InitTypeDef NVIC_InitStructure;
22 　　　　NVIC_InitStructure.NVIC_IRQChannel = WWDG_IRQn; //WWDG  interrupt 
23 　　　　NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; // preemption  2  Sub priority  3  Group  2
24　　　　 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; // preemption  2, Sub priority  3, Group  2
25　　　　 NVIC_Init(&NVIC_InitStructure); //NVIC  initialization 
26 }
27 void WWDG_IRQHandler(void)
28 {
29 　　　　WWDG_SetCounter(WWDG_CNT);
30 　　　　// When this sentence is forbidden , The window watchdog will generate a reset 
31　　　　 WWDG_ClearFlag();
32 　　　　// Clear the early wake-up interrupt flag bit 
33 　　　　LED1=!LED1;
34　　　　 //LED  State flip 
35 }

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Main logical area code ：

 1 int main(void)
 2 {
 3     delay_init();// Delay function initialization 
 4     NVIC_Configuration(); // Set up  NVIC  Interrupt grouping  2
 5     usart1_init(); A serial port 1 initialization 
 6     LED_Init(); //LED  initialization 
 7     KEY_Init(); // Key initialization 
 8     LED0=0;
 9     delay_ms(500);
10     WWDG_Init(0X7F,0X5F,WWDG_Prescaler_8);// The counter value is  7f, The window register is  5f,// The frequency division number is  8
11     while(1)
12     {
13         LED0=1;
14     }
15 }

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Use difference

Let's analyze the independent watchdog （IWDG） And watch dogs （WWDG） The difference between ：

（1） The independent watchdog doesn't stop , There's a break in the window watchdog

（2） Independent watchdog can be divided into hardware and software , The window watchdog can only be controlled by software

（3） Independent watchdog has only a lower limit , Window watchdog has lower limit and upper limit

（4） The independent watchdog is 12 Decreasing bit . The window watchdog is 7 Decreasing bit

（5） The independent watchdog is used inside about 40KHZ RC oscillator , The window watchdog is a system clock APB1ENR

The function does not repeat the description

Function does not repeat , The independent watchdog is used to prevent the system from crashing , The window watchdog is used to ensure the correctness of system operation . For example, a system has a worker thread and a IDLE Threads , When the system is running normally , The worker thread runs 200ms, Pause 100ms. This running sequence must be strictly guaranteed . At this point, you can start a window watchdog in the worker thread , stay IDLE Clear the dog in the thread . If not enough 200ms Just got in IDLE Threads , The worker thread failed to reach the working time , There's a problem , The window watchdog reset is triggered . If exceeded 300ms Not yet in IDLE Threads , Indicates that the worker thread failed to complete in time , It also triggers the window watchdog .

The independent watchdog application is simple , The system must feed the dog before the counter is reset , Otherwise the watchdog triggers , System reset .

In short, that is , The window watchdog is used to ensure the normal operation of the system with known timing , The independent watchdog ensures that the system does not crash , The two watchdog have their own application scenarios , So don't repeat .

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