FPGA based 1080p 60Hz bt1120 interface debugging process record

This BT1120 The interface is in 1080P 60Hz Verified in the video of , When using videos of other frequencies, the corresponding parameters should be modified . In addition, the interface code instantiates a depth bit 512 Of FIFO（quartus）, So when doing simulation test, you need quartus and modelsim Co simulation .

bt1120 The most important part of the interface is the end code and start code （FF 00 00 XYZ）
front 3 Bytes of FF 00 00 It's fixed , The last byte needs to be based on F V H Encoding , When FVH When it's certain P3 P2 P1 P0 It's also certain that . Use 8bit Keep high when the data bit width of 8 position , Round off low 2 position .

Sorted interface


Interface code

/*  Timing reference code  <0xff 0x00 0x00 xxx>
 *  among xxx Is the following value range :
 * 1 0 1 0 1 0 1 1 0 0  0xab( Frame blanking period ,SAV)
 * 1 0 1 1 0 1 1 0 0 0  0xb6( Frame blanking period ,EAV)
 * 1 0 0 0 0 0 0 0 0 0  0x80( Video effective area time ,SAV)
 * 1 0 0 1 1 1 0 1 0 0  0x9d( Video effective area time ,EAV)
 */

`timescale 1ns / 1ps
module ycbcr422_to_bt1120(
    input           rst_n,
    input           clk ,
    input           data_de,
    input           hsync,
    input           vsync,
    input  [15:0]   ycbcr,     
    output          bt1120_pclk,
    output reg [15:0]   bt1120_ycbcr

);

  localparam  BLANKING  =  4'd0; // Blanking stage  //SAV localparam CODE_SAV1 = 4'd1;    // Data start code stage 
  localparam  CODE_SAV2 =  4'd2; localparam CODE_SAV3 = 4'd3;
  localparam  CODE_SAV4 =  4'd4; //EAV localparam CODE_EAV1 = 4'd5;    // Data end code stage 
  localparam  CODE_EAV2 =  4'd6; localparam CODE_EAV3 = 4'd7;
  localparam  CODE_EAV4 =  4'd8; localparam VAILD_VIDEO = 4'd9;    // Data validity stage 



  // Fill in the hidden area of the field STUFF
  localparam  STUFF  = 16'h8010; localparam BSAV = 8'hab;
  localparam BEAV = 8'hb6; localparam VSAV = 8'h80;
  localparam VEAV = 8'h9d; //1080p 60hz localparam WIDTH_TOTAL = 12'd2200 ;   // The width of a line 
localparam   HEIGHT_TOTAL= 12'd1125 ; // The height of a frame  localparam VIDEO_BEFORE_BLANK_NUM = 6'd41 ;   // The number of frame hidden lines before the beginning of a frame 
localparam   VIDEO_AFTER_BLANK_NUM  = 3'd4 ; // The number of frame hidden lines after the end of a frame  localparam BLANK_NUM = 12'd280  ;



wire        full    ;
reg         rd_en   ;
wire[15:0]  rd_data ;
wire        empty   ;

reg [3:0]   state_c ;
reg [3:0]   state_n ; 
wire        blank2sav ;
wire        video2eav ;

reg         data_de0  ;
reg         hsync0    ;
reg         vsync0    ;
reg [15:0]  ycbcr0    ;        
reg         data_de1  ;
reg         hsync1    ;
reg         vsync1    ;
reg [15:0]  ycbcr1    ;
wire        v_pos     ;

reg [11:0]  cnt_h     ;
reg [11:0]  cnt_v     ; 

wire[7:0]   Lumi    ;
wire[7:0]   cbcr ;


assign  bt1120_pclk =  clk ;

yc2bt_fifo yc2bt_fifo_inst0
(
	 .clock (clk     ),
     .data  (ycbcr1  ),
	 .wrreq (data_de1),
	 .full  (full    ),
	 .rdreq (rd_en   ),
	 .q     (rd_data ),
	 .empty (empty   ) 
);

[email protected](posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        state_c <= BLANKING;
    end
    else begin
        state_c <= state_n;
    end
end


[email protected](*)begin
    case(state_c)
        BLANKING:begin
            if(blank2sav)begin
                state_n = CODE_SAV1;
            end
            else begin
                state_n = state_c;
            end
        end
        CODE_SAV1:begin
                state_n = CODE_SAV2;
        end
        CODE_SAV2:begin
                state_n = CODE_SAV3;
        end
        CODE_SAV3:begin
                state_n = CODE_SAV4;
        end
        CODE_SAV4:begin
                state_n = VAILD_VIDEO;
        end
        VAILD_VIDEO:begin
            if(video2eav)begin
                state_n = CODE_EAV1;
            end
            else begin
                state_n = state_c;
            end
        end
        CODE_EAV1:begin
                state_n = CODE_EAV2;
        end
        CODE_EAV2:begin
                state_n = CODE_EAV3;
        end
        CODE_EAV3:begin
                state_n = CODE_EAV4;
        end
        CODE_EAV4:begin
                state_n = BLANKING;
        end        
        default:begin
            state_n = BLANKING;
        end
    endcase
end

assign blank2sav = state_c==BLANKING && cnt_h==12'd275; assign video2eav = state_c==VAILD_VIDEO && cnt_h==12'd2199;


// Input beat 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin data_de0 <= 1'b0 ;
        hsync0   <= 1'b0 ; vsync0 <= 1'b0 ;
        ycbcr0   <= 16'b0 ; end else begin data_de0 <= data_de ; hsync0 <= hsync ; vsync0 <= vsync ; ycbcr0 <= ycbcr ; data_de1 <= data_de0 ; hsync1 <= hsync0 ; vsync1 <= vsync0 ; ycbcr1 <= ycbcr0 ; end end // Get the rising edge of the field signal  assign v_pos = !vsync1 && vsync0 ; // One line counter  always @(posedge clk )begin if(v_pos || cnt_h == WIDTH_TOTAL-1) cnt_h <= 12'b0;
    else 
        cnt_h <= cnt_h + 1;
end

// One frame counter 
always @(posedge clk )begin
    if(v_pos)
        cnt_v <= 12'b0; else if(cnt_h == WIDTH_TOTAL-1)begin if(cnt_v == HEIGHT_TOTAL-1) cnt_v <= 12'b0;
        else
            cnt_v <= cnt_v + 1;
    end                        
end 

// Data 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin bt1120_ycbcr <= STUFF ; end else begin case(state_c) BLANKING:begin bt1120_ycbcr<= STUFF ; end CODE_SAV1:begin bt1120_ycbcr<= 16'hffff ; 
            end
            CODE_SAV2:begin 
                    bt1120_ycbcr<= 16'h0 ; end CODE_SAV3:begin bt1120_ycbcr<= 16'h0 ; 
            end             
            CODE_SAV4:begin
               if(cnt_v<12'd41 ||(cnt_v >= 12'd1121 && cnt_v < 12'd1125)) bt1120_ycbcr<= 16'habab ;
               else if(cnt_v>=12'd41 && cnt_v<12'd1121)
                    bt1120_ycbcr<= 16'h8080 ; end VAILD_VIDEO:begin bt1120_ycbcr<= rd_data ; end CODE_EAV1:begin bt1120_ycbcr <= 16'hffff;
            end
            CODE_EAV2:begin
                    bt1120_ycbcr <= 16'h0; end CODE_EAV3:begin bt1120_ycbcr <= 16'h0;
            end
            CODE_EAV4:begin
               if(cnt_v<12'd41 ||(cnt_v >= 12'd1121 && cnt_v < 12'd1125)) bt1120_ycbcr<= 16'hb6b6 ;
               else if(cnt_v>=12'd41 && cnt_v<12'd1121)
                    bt1120_ycbcr<= 16'h9d9d ; end endcase end end assign Lumi = bt1120_ycbcr[15:8] ; assign cbcr = bt1120_ycbcr[7:0] ; //read en always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin
        rd_en <= 1'b0 ; end else if(cnt_v>=12'd41 && cnt_v < 12'd1121 )begin if(cnt_h>=12'd279 && cnt_h<12'd2200) rd_en <= 1'b1 ;
        else
            rd_en <= 1'b0 ; end else begin rd_en <= 1'b0 ;
    end
end


endmodule

The test file

`timescale 1 ns/1ps

module tb_bt1120();

reg       clk  ;
reg       rst_n;
wire[15:0] ycrcb;
reg       de   ;
reg       vsync;
reg       hsync;
reg[11:0] cnt_h;
reg[11:0] cnt_v;
reg[7:0] lumi ;
reg[7:0] cbcr ;


//uut The output signal of 
wire       bt1120_clk;
wire[15:0] bt1120_data;

// Clock cycle , Unit is ns, You can modify the clock cycle here .
parameter CYCLE    = 7;

// Reset time , At this time, it means reset 3 The time of a clock cycle .
parameter RST_TIME = 20 ;


ycbcr422_to_bt1120 u_ycbcr422_to_bt1120(
    .rst_n   (rst_n ), //input         
    .clk     (clk   ), //input          
    .data_de (de    ), //input [15:0]   
    .hsync   (hsync ), //input          
    .vsync   (vsync ), //input          
    .ycbcr   (ycrcb ), //input          
  
   //bt.1120 Interface 
    .bt1120_pclk (bt1120_clk ) , //output           
    .bt1120_ycbcr(bt1120_data)   //output reg[15:0] 

    );
//1080P 60Hz
parameter   h_total  = 12'd2200; parameter hsync_pw = 6'd44   ;  // Line blanking pulse width , In units of clock 

parameter   v_total  = 12'd1125; parameter vsync_pw = 3'd5    ;  // Line blanking pulse width , Behavior unit 

parameter   data_f_enabel = 6'd42 ; // The first row of valid data , Behavior unit  parameter data_e_enabel = 12'd1120;  // The last line of valid data , Behavior unit 

parameter   data_de_start = 8'd192 ; // Data valid start , In units of clock  parameter data_de_end = 12'd2112;  // Data valid end , In units of clock 

// Generate local clock 50M
initial begin
    clk = 0;
    forever
    #(CYCLE/2)
    clk=~clk;
end

// Generate reset signal 
initial begin
    rst_n = 1;
    #2;
    rst_n = 0;
    #(CYCLE*RST_TIME);
    rst_n = 1;
end

// A counter for a row of data 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin cnt_h <= 12'b0 ;
    end
    else begin
        if(cnt_h == h_total-1)
            cnt_h <= 12'b0 ; else cnt_h <= cnt_h + 1 ; end end // A counter for one frame of data ,1080P 60hz A frame of data is 1125 That's ok  always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin
        cnt_v <= 12'b0 ; end else if(cnt_h == h_total-1)begin if(cnt_v == v_total-1) cnt_v <= 12'b0 ;
        else
            cnt_v <= cnt_v + 1 ;
    end
end

// Generate line signal 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin hsync <= 1'b0 ;
    end
    else if(cnt_h < hsync_pw  )begin
        hsync <= 1'b1 ; end else begin hsync <= 1'b0 ;
    end
end

// Generate field signals 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin vsync <= 1'b0 ;
    end
    else if(cnt_v < vsync_pw  )begin
        vsync <= 1'b1 ; end else begin vsync <= 1'b0 ;
    end
end

// Generate data valid signals 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin de <= 1'b0 ;
        lumi <= 8'b0; cbcr <= 8'b0;
    end
    else if(cnt_v >= data_f_enabel-1 && cnt_v <= data_e_enabel)begin
        if(cnt_h >= data_de_start-1 && cnt_h < data_de_end-1 )begin
            de   <= 1'b1 ; lumi <= lumi+1; cbcr <= cbcr+1; end else begin de <= 1'b0 ;
            lumi <= 8'b0; cbcr <= 8'b0;
        end
    end
end

assign ycrcb = {
    lumi,cbcr} ;

endmodule