Verilog realizes serial communication and sends it to the nixie tube

verilog Realize serial communication , Realization PC And FPGA Serial port communication , Key digital tube display .
clock frequency 50MHZ, Baud rate 115200, Adjustment can be modified .
Serial port input data , Send it to the nixie tube for display .

stay vivado Build the project and integrate ：

The top module code is as follows ：

`timescale 1ns / 1ps
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// Create Date:
// Design Name:
// Module Name: uart_disp_top
// Project Name:
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// Description:
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// Dependencies:
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// Revision:
// Revision 0.01 - File Created
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module uart_disp_top(
input clk, //clock input
input rst_n, //asynchronous reset input, low active
input rx_pin, //serial data input

output [5:0]       Scan_Sig,// Bit selection signal     We only use two nixie tubes here 
output  [7:0]SMG_Data
);

wire [7:0] data1;
//wire [7:0] da