MC Instruction Decoder

Instruction Decoder

MC Instruction Decoder Belong to MC layer LLVM Disassembly module in , The main function is to read and write the input binary file as Bytes form , The output corresponds to Target Machine instructions MCInst, Is an indispensable module in disassembly :

MCDisassembler class  

 MCDisassembler Class is MC Instruction Decoder Improved interface classes in and out , Belong to all target disassembler Of superclass,

This class is located in ：llvm\include\llvm\MC\MCDisassembler\MCDisassembler.h file

This class has few interfaces , One of the most important interfaces ：getInstruction:

virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
                                      ArrayRef<uint8_t> Bytes, uint64_t Address,
                                      raw_ostream &CStream)

This interface converts executable binaries to Bytes As input , Input through disassembly MCInst Machine instructions .

This interface is a virtual function , Every target Machine instructions are different , Writing a new backend requires MCDisassembler Base class , Derive from target Corresponding disassembler, Realization getInstruction Interface .

AMDGPU The derivation relationship is as follows ：

AMDGPUDisassembler be located llvm\lib\Target\AMDGPU\Disassembler\AMDGPUDisassembler.h

 Disassembler Usage method

disassembler The usage method is usually divided into the following steps ：

RegisterMCDisassembler（）

When a new backend is added , Need to call RegisterMCDisassembler towards Target Registered in disassemble, AMDGPU Registered at llvm\lib\Target\AMDGPU\Disassemble\AMDGPUDisassembler.cpp： 

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() {
  TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
                                         createAMDGPUDisassembler);
  TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
                                       createAMDGPUSymbolizer);
}

 RegisterMCDisassembler The main registration corresponds to establish disassamble Callback function createAMDGPUDisassembler.

static void RegisterMCDisassembler(Target &T,
                                     Target::MCDisassemblerCtorTy Fn) {
  T.MCDisassemblerCtorFn = Fn;
}

establish disassembler The callback function is registered to MCDisassemblerCtorFn.

createMCDisassembler

createMCDisassembler Create the corresponding MCDisassembler:

MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI,
                                     MCContext &Ctx) const {
  if (!MCDisassemblerCtorFn)
    return nullptr;
  return MCDisassemblerCtorFn(*this, STI, Ctx);
}

  Call registered createAMDGPUDisassemble Callback function , establish AMDGPUDisassembler.

getInstruction

The parsed binary file Text Code segment , Turn into ArrayRef<uint8_t>, Disassembly , for example ：

MCInst Inst;
bool Disassembled =
DisAsm->getInstruction(Inst, Size, Bytes.slice(Index),
                        SectionAddr + Index, CommentStream);

 AMDGPU getInstruction()

AMDGPU The disassembly implementation is located at llvm\lib\Target\AMDGPU\Disassembler\AMDGPUDisassembler.cpp file ：

The implementation process is relatively clear , Disassembly is mainly divided into two parts ：

• First, disassemble the binary , Look for all kinds of DecoderTable surface , Find the instruction to which the binary belongs . The characteristic of this step is to check DecoderTable surface ,AMDGPU According to different architecture instructions and instruction types, it is divided into multiple DecoderTable surface , Step by step matching is required .
• After matching , Further processing for some special instructions .

DecoderTable

AMDGPU Back end to support disassembly , Internally, the command is divided into multiple DecoderTable,getInstruction Each... Will be matched and queried in turn DecoderTable Table to match , Exist at present DecoderTable There are mainly ：

• DecoderTableGFX10_B64
• DecoderTableDPP864
• DecoderTableDPP64
• DecoderTableSDWA64
• DecoderTableSDWA964
• DecoderTableSDWA1064
• DecoderTableGFX80_UNPACKED64
• DecoderTableGFX832
• DecoderTableAMDGPU32
• DecoderTableGFX932
• DecoderTableGFX90A32
• DecoderTableGFX10_B32
• DecoderTableGFX1032
• DecoderTableGFX90A64
• DecoderTableGFX864
• DecoderTableAMDGPU64
• DecoderTableGFX964
• DecoderTableGFX1064

above DecoderTable Yes TableGen Automatically generate to... During the compilation phase build/lib/Target/AMDGPU/AMDGPUGenDisassemblerTables.inc In file , Generate commands manually ：

llvm-tblgen -gen-disassembler./AMDGPU.td -I ../../../include

With DecoderTableGFX932 For example, GFX 32 position  DecoderTable surface ：

 

The beginning of each line MCD::OPC_XXXX Is the corresponding status , And determine the significance of subsequent numerical values

For example, the beginning MCD::OPC_ExtractField follow-up 25,7 Jump to the start and end of the match for the next step ,start=25, end=31.

decodeInstruction

decodeInstruction Based on the DecoderTable surface , Disassemble and decode , be located build/lib/Target/AMDGPU/AMDGPUGenDisassemblerTables.inc In file ,

According to the matching table MCD::OPC_XXXX Match operation , until MCD::OPC_Decode The status description is in this DecoderTable Table matching succeeded , otherwise MCD::OPC_Fail Matching failure , Try the next DecoderTable Table to match

  Here is an example ：

/* 62 */      MCD::OPC_Decode, 236, 127, 46, // Opcode: V_ADDC_CO_U32_e32_gfx9

236,127 Solve the corresponding... For the corresponding opcode, The highest number 8 individual bit Bit flag bit , When the setting represents the opcode Greater than 128 It needs to be split into multiple , Until the highest position is not 1 until , The calculation method is as follows ：

（236&~128）+ 127<<7

 46 Corresponding DecodeIdx,decodeToMCInst Decide to follow up operand Register parsing operation ：

Eventually the machine instructions will be disassembled MCInst.