SPI interface introduction -piyu dhaker

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SPI Interface profile author ： Piyu Dhaker

• Serial peripheral interface (SPI) Microcontrollers and peripherals IC（ Such as sensor 、ADC、DAC、 shift register 、SRAM etc. ） One of the most widely used interfaces between . This article begins with a brief description SPI Interface , Then introduce ADI The company supports SPI Analog switches and multiplexers , And how they help reduce the number in the system circuit board design GPIO Number .
• SPI It's a kind of synchronization 、 full duplex 、 Master slave interface . The data from the master or slave is synchronized on the rising or falling edge of the clock . The master and slave can transmit data at the same time .SPI The interface can be 3 Linear or 4 Linear type . This paper focuses on the commonly used 4 Line SPI Interface . Interface

chart 1. Including master and slave SPI To configure . 4 Line SPI The device has four signals ： The clock (SPI CLK, SCLK) Chip selection (CS) Host output 、 Slave input (MOSI) Host input 、 Slave output (MISO)

• The device that generates the clock signal is called the host . The data transmitted between the master and the slave is synchronized with the clock generated by the master . Same as I2C Interface comparison ,SPI The device supports a higher clock frequency . Users should refer to the product data manual for SPI Clock frequency specification of the interface .
• SPI The interface can only have one host , But there can be one or more slaves . chart 1 Shows the connection between the master and the slave SPI Connect .
• The chip selection signal from the host is used to select the slave . This is usually a low level active signal , When pulling up, the slave and SPI The bus is disconnected . When using multiple slaves , The master needs to provide a separate chip selection signal for each slave . The chip selection signal in this paper is always a low-level effective signal .
• MOSI and MISO It's the data line .MOSI Send data from the host to the slave ,MISO Send data from slave to host . The data transfer To start SPI signal communication , The host must send a clock signal , And by enabling CS Signal selection slave . Chip selection is usually a low-level active signal . therefore , The host must send logic on this signal 0 To select the slave .SPI It's a full duplex interface , The master and slave can pass through MOSI and MISO The line sends data at the same time . stay SPI During the communication , Data transmission （ Serial move out to MOSI/SDO On the bus ） And receiving （ Sample or read into the bus (MISO/SDI) The data on the ） At the same time . The serial clock is shifted and sampled along the synchronous data .SPI The interface allows users to flexibly select the rising edge or falling edge of the clock to sample and output / Or shift data . To be sure to use SPI The number of data bits transmitted by the interface , Refer to the device data manual . Clock polarity and clock phase * stay SPI in , The host can select clock polarity and clock phase . During idle state ,CPOL Bit sets the polarity of the clock signal . The idle state is when the transmission starts CS It is high level and during the transition to low level , And at the end of the transmission CS It is low level and during the transition to high level .CPHA Bit selects the clock phase . according to CPHA Bit status , Use the rising or falling edge of the clock to sample and / Or shift data . The master must select the clock polarity and clock phase according to the requirements of the slave . according to CPOL and CPHA The choice of bits , There are four kinds. SPI Mode available . surface 1 Shows this 4 Kind of SPI Pattern . surface 1. adopt CPOL and CPHA choice SPI Pattern

chart 2 To 5 Four... Are shown SPI Example of communication in mode . In these examples , The data is shown in MOSI and MISO on-line . The beginning and end of transmission are indicated by green dotted lines , The sampling edge is represented by an orange dotted line , The shift edge is indicated by a blue dotted line . Please note that , These figures are for reference only . To succeed SPI signal communication , The user must refer to the product data manual And ensure that the timing specification of the device is met .

chart 2. SPI Pattern 0,CPOL = 0,CPHA = 0：CLK Idle state = Low level , The data is sampled on the rising edge , And move out on the falling edge .

chart 3. SPI Pattern 1,CPOL = 0,CPHA = 1：CLK Idle state = Low level , The data is sampled on the falling edge , And move out on the rising edge .

chart 4. SPI Pattern 2,CPOL = 1,CPHA = 1：CLK Idle state = High level , The data is sampled on the falling edge , And move out on the rising edge .

chart 5. SPI Pattern 3,CPOL = 1,CPHA = 0：CLK Idle state = High level , The data is sampled on the rising edge , And move out on the falling edge .

• chart 3 given SPI Pattern 1 Sequence diagram . In this mode , The clock polarity is 0, Indicates that the idle state of the clock signal is low . The clock phase in this mode is 1, Indicates that the data is sampled on the falling edge （ Displayed by orange dotted line ）, And the data is in the... Of the clock signal The rising edge moves out （ Shown by a blue dotted line ）.
• chart 4 given SPI Pattern 2 Sequence diagram . In this mode , The clock polarity is 1, Indicates that the idle state of the clock signal is high . The clock phase in this mode is 1, Indicates that the data is sampled on the falling edge （ Displayed by orange dotted line ）, And the data is in the... Of the clock signal The rising edge moves out （ Shown by a blue dotted line ）. * chart 5 given SPI Pattern 3 Sequence diagram . In this mode , The clock polarity is 1, Express The idle state of the clock signal is high . The clock phase in this mode is 0, Indicates that the data is sampled on the rising edge （ Displayed by orange dotted line ）, And the data is in the... Of the clock signal The falling edge moves out （ Shown by a blue dotted line ）. Multi slave configuration
• Multiple slaves can work with a single slave SPI Use with the host . The slave can be connected in normal mode , Or daisy chain connection .

chart 6. Multi slave SPI To configure . routine SPI Pattern ： In normal mode , The master needs to provide a separate chip selection signal for each slave . Once the host is enabled （ Pull it down ） Piece of optional signal , MOSI/MISO The clock and data on the line can be used for the selected slave . If multiple chip selection signals are enabled , be MISO Online data will be destroyed , Because the host cannot recognize which slave is transmitting data . From the picture 6 It can be seen that , As the number of slaves increases , The number of chip selection lines from the host also increases . This will quickly increase the number of inputs and outputs that the host needs to provide , And limit the number of slaves that can be used . Other technologies can be used to increase the number of slaves in normal mode , For example, a multiplexer is used to generate a chip selection signal . Daisy chain mode ：

chart 7. Multi slave SPI Daisy chain configuration . In daisy chain mode , The chip selection signals of all slaves are connected together , Data is propagated from one slave to the next . In this configuration , All slaves receive the same message at the same time SPI The clock . The data from the master is sent directly to the first slave , The slave provides data to the next slave , And so on . When this method is used , Because data is propagated from one slave to the next , Therefore, the number of clock cycles required to transmit data is proportional to the slave position in the daisy chain . For example, in figure 7 Shown 8 Bit system , In order to make the second 3 A slave can get data , need 24 Clock pulses , And conventional SPI In mode, just 8 Clock pulses . chart 8 Shows the clock cycle and data propagation through the daisy chain . Not all SPI All devices support daisy chain mode . Refer to the product data manual to confirm that the daisy chain is available .

chart 8. Daisy chain configuration ： Data dissemination . ADI The company supports SPI Analog switches and multiplexers

• ADI The company's latest generation supports SPI The switch can be used without affecting the performance of precision switch Significantly save space . This part of this article will discuss a case study , explain Support SPI How switches or multiplexers can greatly simplify system level design and reduce Less needed GPIO Number .
• ADG1412 It's a four channel 、 Single throw (SPST) switch , We need four GPIO Connect Control input to each switch . chart 9 Shows the microcontroller and a ADG1412 And The connection between .

chart 9. Micro controller GPIO Used as the control signal of the switch

• As the number of switches on the circuit board increases , what is needed GPIO The number of will also increase significantly . for example , When designing a test instrument system , A large number of switches will be used to increase the number of channels in the system . stay 4×4 Intersection matrix configuration , Use four ADG1412. This system requires 16 individual GPIO, Limited availability in standard microcontrollers GPIO. chart 10 Shows the of using microcontroller 16 individual GPIO Connect four ADG1412.
• In order to reduce the GPIO Number , One way is to use a serial to parallel converter , Pictured 11 Shown . The parallel signal output by the device can be connected to the switch control input , Device can Through serial interface SPI To configure . The disadvantage of this method is that additional devices will cause material cleaning Single increase .
• Another way is to use SPI Control switch . The advantage of this method is that it can reduce the need GPIO The number of , And it can also eliminate the overhead of additional serial to parallel converter . Pictured 12 Shown , Unwanted 16 A microcontroller GPIO, It only needs 7 A microcontroller GPIO Can be In order to 4 individual ADGS1412 Provide SPI The signal .
• Switches can be daisy chained , To further optimize GPIO Number . Configure in daisy chain in , No matter how many switches the system uses , Only use the host （ Micro controller ） Four of four individual GPIO.

chart 10. In a multi slave configuration , what is needed GPIO A substantial increase in the number of .

chart 11. Multi slave switch using serial to parallel converter .

chart 12. Support SPI Open joint saving microcontroller GPIO.

chart 13. Daisy chain configuration SPI The switch can be further optimized GPIO.

• chart 13 For illustrative purposes . ADGS1412 The data book suggests that SDO A pin is used A pull-up resistor . For more information about daisy chain patterns , see also ADGS1412 data manual . For the sake of simplicity , This example uses four switches . With the number of switches in the system An increase in quantity , The advantages of simple circuit board and space saving are very important . stay 6 Layer circuit board Put... On top of 8 Four channels SPST switch , use 4×8 When configuring intersections , ADI Company branch a SPI The switch can save 20% Total board space . article “ precision SPI Switch configuration Increase channel density ” Detailed description of precision SPI How does the switch configuration improve the channel density .
• ADI The company provides a variety of support SPI Analog switches and multiplexers . For more information , Please visit here .

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