(5) SPI application design and simulation verification 2 - design code implementation

 （ Two ） Code implementation

 1） Practical code ——master

module spi_master(
    input        clk,
    input        rstn,
    input[11:0]  cmd_in,
    input        cmd_valid,
    input        miso,

    output       sclk,
    output       csn,
    output       mosi,
    output       cmd_ready,
    output[7:0]  read_data,
    output       read_valid
);

parameter        BAUD_NUM = 200/10;

reg[7:0]         baud_cnt_r;
wire             baud_cnt_half = baud_cnt_r == (BAUD_NUM>>1) - 1;
wire             baud_cnt_end  = baud_cnt_r == BAUD_NUM - 1;
reg[7:0]         read_data_r;
reg              read_valid_r;
reg[3:0]         bit_cnt_r;
reg[11:0]        cmd_in_r;
reg              cmd_ready_r;
reg              csn_r;
reg              sclk_r; 
reg              mosi_r;  

//(1)sclk    
[email protected](posedge clk or negedge rstn) begin
    //state0： Reset and clear 
    if(!rstn) begin
        sclk_r    <= 'b0;
    end