[bus interface] Axi interface

AXI Introduce ：

What is? AXI?

AXI（ Advanced extensible interface ）： yes ARM AMBA Part of .

AMBA（ Advanced microcontroller bus architecture ）： yes 1996 A set of microcontroller buses first introduced in ; Open on-chip interconnect bus standard , It can realize the connection and management between multiple controllers and peripheral devices in multi host system .

AXI Three types of interfaces ：

• AXI4(AXI-Full)： Memory mapping requirements for high performance ;

notes ： Memory mapping ： When the host reads and writes to the slave , Specify a destination address , This address corresponds to the address of the system storage space , It means to read and write the space . It is generally used for the transmission of large amounts of data .

• AXI4-Lite： A simplified version of AXI4 Interface , Communication for low throughput memory mapping , Generally used for register configuration 、 Reading and writing, etc .
• AXI4-Stream（ST）： For high-speed streaming data communication . It is generally used for the transmission of video stream information .

Differences among the three ：AXI4 and AXI4-Lite All belong to memory mapped interfaces , When communicating with these two interfaces , The host needs to specify the address for reading and writing ; and AXI-Stream Time stream data , There is no need to specify the address for reading and writing .AXI4 It has the most functions , And it takes up the most resources ;AXI4-Lite Equivalent to a comprehensive simplification AXI4 Interface ;AXI-Stream Not a memory mapped interface , For data transmission .

AXI The advantages of ：

• Productivity
• flexibility
  • AXI4（ Support the unexpected 256 Data ） Memory belongs to
  • AXI4-Lite（ You can only transmit 1 Data ） Memory belongs to ;
  • AXI-Stream Not a memory map , Its burst length is unlimited .
• Availability

AXI How it works ：

 

AXI4 and AXI-Lite contain 5 It's a separate channel

• Read address channel
• Write address channel
• Read data channel
• Write data channel
• Write response channel

AXI4： Because the read and write address channels are separate , Therefore, it supports two-way simultaneous transmission ; The maximum burst length is 256;

AXI4-Lite： and AXI4 similar , However, burst transmission is not supported ;

AXI4-Stream： There is only one single data channel , and AXI4 The write data of is similar , Its burst length is unlimited .

AXI InterConnect and AXI SmartConnect：

these two items. IP Cores are used to connect single / Multiple memory mapped AXI Master And Dan / Multiple memory mapped AXI Slave, Can be used to connect AXI4 and AXI-Lite, But it can't connect AXI-Stream, Because it is not a memory mapped interface .

 

The connection form can be ：

• one-on-one
• For one more
• One to many
• Many to many

When many to one, you need to arbitrate in the interconnection module , Decide which host data is transferred to the slave ;

When one to many, you need to route in the interconnection module , Decide which slave the data of the host is transferred to ;

AXI Channel definition for ：

Each independent channel contains a set of information signals 、VALID Signals and READY The signal , Used to provide a two-way handshake mechanism .

The information source side uses VALID The signal indicates the current channel address 、 When data and control signals are valid ;

Target end use READY The signal indicates when information can be received ;

Both the read data channel and the write data channel contain a LAST The signal , Used to represent the last data transmitted .

Both read and write data channels contain their own address channels , The address channel carries the address and information required for the request ;

The read data channel is sent from the slave to the host , It contains the information of reading data and reading response , The signal of read response is used to indicate whether the read transmission operation is completed ;

The write data channel is sent by the host to the slave , Contains write data , And then through WSTRB The signal indicates which byte of the current data is valid ;

The write response channel is sent from the slave to the host , Contains the write response signal , Used to indicate whether the current write operation is completed .