RMII, smii, gmii, rgmii interfaces of Ethernet Driver

        The last chapter talked about MII Although the interface is very flexible , However, there is a disadvantage because the signal line used for one port has 14 Many roots , If one 8 Port switches need to use 112 Root line ,16 The port will be used 224 Root line , To 32 The port is used 448 Root line . Generally, it is unrealistic to make a switch according to this interface . Therefore, the production of modern switches will use others from MII Simplified standards , such as RMII、SMII、GMII etc. .

MII

MII（Media Independent interface） Media independent interface , It is IEEE-802.3 Defined industry standards , yes MAC And PHY Interface between .MII The data interface contains 16 A signal and 2 A management interface signal , As shown in the figure below ：

The signal is defined as follows ：

         MAC adopt MII Interface read PHY Status register to know the current PHY The state of . For example, connection speed 、 Duplex capability, etc . It can also be done through MII Set up PHY To achieve the purpose of control . For example, opening and closing of flow control 、 Self negotiation mode or compulsory mode, etc .MII With 4 Two way data transmission in bit nibble mode , Clock speed 25MHz, Its working speed can reach 100Mb/s; The clock frequency was 2.5MHz when , The corresponding rate is 10Mb/s.

RMII

RMII(Reduced Media Independant Interface), Streamlining MII Interface , Save half the data cable .RMII Send and receive using 2 Bit data for transmission , The receiving and transmitting clocks all adopt 50MHz Clock source . The signal is defined as follows ：

among CRS_DV yes MII in RX_DV and CRS Combination of two signals , When the physical layer receives the carrier signal CRS_DV Become effective , Send the data to RXD. When the carrier signal disappears ,CRS_DV Will become invalid . stay 100M Ethernet rate medium ,MAC The layer samples once per clock RXD[1:0] The data on the , stay 10M Ethernet rate medium ,MAC Each layer 10 Sampling once per clock RXD[1:0] The data on the , At this time, each data received by the physical layer will be in RXD[1:0] Retain 10 A clock .

SMII

SMII（Serial Media Independant Interface）, Serial MII Interface . It includes TXD,RXD,SYNC Three signal lines , Share a clock signal , The clock signal is 125MHz, The signal line is synchronized with the clock . The signal is defined as follows ：

SYNC It is the synchronization signal of data transmission and reception , Every time 10 The two clocks are synchronously set to the high level , Synchronous representation .TXD and RXD Data and control information on , With 10bit For a group . The waveform of the transmission part is as follows ：

It can be seen from the waveform that ,SYNC After getting higher 10 In clock cycles ,TXD Output a set of... In turn 10bit That is TX_ER,TX_EN,TXD[0:7], These control information and MII Interface has the same meaning . stay 100M In the rate , The content of each group is transformed , stay 10M In the rate , Each set of data needs to be repeated 10 Time , Any group of samples can .

GMII

GMII（Gigabit Media Independant Interface）, Gigabit MII Interface .GMII use 8 Bit interface data , Working clock 125MHz, So the transmission rate can reach 1000Mbps. Compatible with MII Required 10/100 Mbps Operation mode .GMII Interface data structure conforms to IEEE Ethernet standard , The interface is defined in IEEE 802.3-2000. The signal is defined as follows ：

RGMII

RGMII(Reduced Gigabit Media Independant Interface), Streamlining GMII Interface . be relative to GMII comparison ,RGMII Has the following characteristics ：

    send out / The receiving data line is provided by 8 Change article to 4 strip
    TX_ER and TX_EN Reuse , adopt TX_CTL delivery
    RX_ER And RX_DV Reuse , adopt RX_CTL delivery
    1 Gbit/s At a rate , The clock frequency is 125MHz
    100 Mbit/s At a rate , The clock frequency is 25MHz
    10 Mbit/s At a rate , The clock frequency is 2.5MHz
The signal is defined as follows ：

although RGMII The signal line is halved , but TXC/RXC The clock is still 125Mhz, In order to achieve 1000Mbit The transmission rate of ,TXD/RXD The signal line sends and receives at the rising edge of the clock GMII Interface TXD[3:0]/RXD[3:0], Send and receive at the falling edge of the clock TXD[7:4]/RXD[7:4], And the signal TX_CTL Responded to TX_EN and TX_ER state , That is to say TXC The rising edge sends TX_EN, The falling edge sends TX_ER, The same applies to RX_CTL, The following figure shows the timing of sending and receiving ：