LLVM TargetPassConfig

TargetPassConfig

TargetPassConfig Class is LLVM Back end add pass entrance ,LLVM The framework divides the whole back end into instruction selection 、 Instruction scheduling , Register allocation, etc ,, Here's the picture ：

Each of these phases contains one or more pass,LLVM One of the most important processes in the backend is compatibility and modularity , To add to these back ends pass Conduct management ,LLVM The back end encapsulates the interfaces for the above important stages , Each interface basically represents one Important stage , Every target You can add as many as you need pass,

TargetPassConfig The class for codegen Various interfaces are provided for each stage in , The main interfaces provided are as follows ：

Interface	explain
addISelPasses	Add all necessary from llvm IR Convert to generation MI Of pass
addIRPasses	Add pair llvm IR->IR The optimization of the pass
addPassesToHandleExceptions	Add various exceptions at lower levels pass, these pass Main treatment CodeGen Various exceptions generated in
addCodeGenPrepare	stay LLVM IR Add... To this level CodeGen I've been preparing for pass, these pass At this time, only IR, So you need to addPassesToHandleExceptions Before adding
addISelPrepare	Add some optimizations before instruction selection IR Of pass, This stage is also in IR Stage , Not converted to DAG, Main optimization IR
addInstSelector	Add instruction selector selector And if necessary pass
addIRTranslator	add to IR Convert to machine code related pass, When calling a relationship addIRTranslatoràaddInstSelector
addMachinePasses	Add a set CodeGen Required by the standard pass
addMachineSSAOptimization	SSA Optimization needs to add pass
addPreRegAlloc/addPostRegAlloc	Before register allocation / You need to add pass
addFastRegAlloc	To quickly allocate registers, you need to add pass

addPassesToGenerateCode

addPassesToGenerateCode Function to add CodeGen Pass The main entrance ：

/// addPassesToX helper drives creation and initialization of TargetPassConfig.
static TargetPassConfig *
addPassesToGenerateCode(LLVMTargetMachine &TM, PassManagerBase &PM,
                        bool DisableVerify,
                        MachineModuleInfoWrapperPass &MMIWP) {
  // Targets may override createPassConfig to provide a target-specific
  // subclass.
  TargetPassConfig *PassConfig = TM.createPassConfig(PM);
  // Set PassConfig options provided by TargetMachine.
  PassConfig->setDisableVerify(DisableVerify);
  PM.add(PassConfig);
  PM.add(&MMIWP);

  if (PassConfig->addISelPasses())
    return nullptr;
  PassConfig->addMachinePasses();
  PassConfig->setInitialized();
  return PassConfig;
}

•  createPassConfig ： according to PM Create the corresponding target Of   TargetPassConfig , Every target Will be based on this class , Re implement the important interfaces in the phase to add unique pass, It doesn't affect the others target
• PassConfig->addISelPasses: Add what is required in the instruction selection phase pass The main entrance
•  PassConfig->addMachinePasses(): Instructions from IR After converting to machine code , Added pass, Including register allocation , And machine code level optimization pass etc.

AMDGPU TargetPassConfig

When writing a new backend , An important content is to realize this target Add as needed pass, With AMDGPU For example TargetPassConfig The inheritance relationship is as follows ：

•  AMDGPUPassConfig： It's all AMDGPU The backend must be added pass
• GCNPassConfig and  R600PassConfig They are aimed at GCN and R600 platform .