Exploration of 6-wire SPI transmission mode

Hardware environment

        4G modular ：FIBOCOM_AL940, be based on MDM9628 CordX-A7 1.3 GHz Single core ,RAM 70M ROM 150M, Contains two groups spi Interface , Only the main equipment , The biggest support 50M Clock speed ;

        MCU Single chip microcomputer ：RH850/F1K, Contains two groups spi Interface , Support master-slave mode ; Maximum support from mode 5M Clock speed ;

        4G Module dominated mode , Single chip microcomputer as slave device ,4 Line spi Add 2 Synchronization line ,master_ready Output ,slave_ready Input ;

Host timing

        From the machine through s_r From low to high level changes, the host is notified to send a clock signal , Both parties negotiate the number of clocks 4K data , The host changes m_r The status notification starts from the machine clock signal ：

  Commissioning process

        Red thread s_r Pin , After the rising edge triggers an interrupt , The clock signal didn't come out , But when the falling edge comes out , At this time, the MCU sends a byte of data ：

          After sending a byte of data, you don't continue to send data , This is very unusual .

        Check the SCM 6 Line spi The mode instruction manual is as follows ,CSIHTRYO Pin as output , Low level busy state , High level transceiver data status , So the rising edge triggers 4G The module sends a clock signal ：

          But from the waveform diagram 4G The module does not send the clock according to the rising edge , Instead, the falling edge sends the clock , So it needs to be modified spi Drive to adapt to the timing requirements of MCU .

        see 4G Modular spi The driving is that the rising edge triggers an interrupt to send and receive data , How can the modified drive be triggered by the falling edge , There was no doubt or confirmation at that time, which led to the problem .

      gpio_direction_input(fibo_spidev->gpio_slave_ready); //SPI_SRDY has external pull-up
     
	  status = request_irq(gpio_to_irq(fibo_spidev->gpio_slave_ready), spidev_slave_ready_irq_handler,
                                            IRQF_TRIGGER_RISING | IRQF_DISABLED, "ql-spi", fibo_spidev);
        if (status) {
            printk("Fail to request gpio_slave_ready IRQ\n");
        } else {
            fibo_spidev->irq_slave_ready = gpio_to_irq(fibo_spidev->gpio_slave_ready);
            disable_irq(fibo_spidev->irq_slave_ready);
        }
    }

Problem solving

        4G modular spi The drive is modified to trigger the sending of clock signal to start data transmission and reception on the rising edge ,6 The line function is normal , but m_r Pins are not used , SCM can send and receive normally without managing this state , At present, there is no probability of packet loss in one night of testing .