[notes] some records of 74hc573

In some nixie tubes that need to latch signals , You can often see 74HC573. Use 74HC573 It can save the use of our pins .

74HC573 Is a transparent latch with eight outputs , The output is a three state gate , It is a high performance silicon gate CMOS device .
Pictured ,OE by The three states allow the control end ( Low level active ), It is often called output Enable end .
1D–8D For data input ; 1Q–8Q For data output terminal ;LE by Latch permissive end , Or latch the control end .

Its internal schematic diagram ：

Truth table

The graph is 74HC573 Truth table of , The meaning of the letter code in the truth table is as follows :
H I high level ,
L A low level ;
Lowercase h、l The level state saved for the moment of departure
X An arbitrary level ,
Z A high resistance state output
QO Last level state .
NC— unchanged , When the state lock changes from high to low

As can be seen from the truth table ：

When OE For low ,LE When you are high ,Dn The input level status is high ,On The output status is high ,Dn The input level status is low ,On The output status is low .

When OE For low ,LE When it's low ,Dn The level state of is high before leaving ,On The output status is high ,Dn The level state of is low before leaving ,On The output status is low .

When OE For low ,LE When it's low ,Dn The level state of does not change before leaving (X),On The state of the output does not change ,On When the state lock changes from high to low .

When OE For the high ,LE When you are high ,Dn The input level status is high ,On The output state is the high-level state of the high resistance state ,Dn The input level status is low ,On The output state is the high-level state of the low resistance state . The high resistance state can be understood as , Basically no output ！

When OE For the high ,LE When it's low ,Dn The level state is high before leaving ,On The output state is the high-level state of the high resistance state ,Dn The level state of is low before leaving ,On The output state is the high-level state of the low resistance state . The high resistance state can be understood as , Basically no output ！

LE For the high time , It will not be locked , in other words On Input what ,Dn Just output something .
OE Select the signal for the film , When OE For the low , The latch is in normal working state , When OE For the high time , The latch is in the high resistance state （ No output , It is equivalent to not enabling ）.