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IP Core: PLL

2022-07-26 00:15:00 【Liu Yaner】

Preface

Software version ：Quartus17.1

Text

One 、 To configure

notes ： What I have here PLL The output clock does not involve frequency doubling and frequency division , If you want to configure frequency multiplication and frequency division clock , You can refer to Wildfire - B Stop video - PLL Frequency division and multiplication
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Two 、 call

Find the created folder IP nucleus
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After opening ：

ly_pll	ly_pll_inst (
	.areset ( areset_sig ),
	.inclk0 ( inclk0_sig ),
	.c0 ( c0_sig ),
	.c1 ( c1_sig ),
	.c2 ( c2_sig ),
	.locked ( locked_sig )
	);

Copy the above code to the top , After changing the connection port ：

ly_pll	ly_pll_inst
(
    .areset (~sys_rst_n     ),
    .inclk0 (sys_clk        ),
    .c0     (clk_125m       ),
    .c1     (clk_125m_shift ),
    .c2     (clk_25m        ),
    .locked (locked1        )
);