Verilog expression

Verilog expression

expression

Expressions consist of operators and operands , The purpose is to get a calculation result according to the meaning of the operator . Expressions can be used anywhere a value appears . for example ：

example

a^b ;          //a And b To perform exclusive or operations
address[9:0] + 10'b1 ;  // Address accumulation
flag1 && flag2 ;  // Logic and operation

Operands

Operands can be any data type , Only certain syntactic structures require the use of certain types of operands .

Operand can be constant , Integers , The set of real Numbers , Wire network , register , Time , Biting , Domain selection , Memory and function call, etc .

example

module test;

// The set of real Numbers
real a, b, c;
c = a + b ;

// register
reg  [3:0]       cprmu_1, cprmu_2 ;
always @(posedge clk) begin
        cprmu_2 = cprmu_1 ^ cprmu_2 ;
end
         
// function
reg  flag1 ;
flag = calculate_result(A, B);
 
// Illegal operand
reg [3:0]         res;
wire [3:0]        temp;
[email protected] （*）begin
    res    = cprmu_2 – cprmu_1 ;
    //temp = cprmu_2 – cprmu_1 ; // illegal ,always The assignment object in a block cannot be wire type
end

endmodule

The operator

Verilog About 9 Operators , They are arithmetic 、 Relationship 、 Equivalent 、 Logic 、 Bitwise 、 reduction 、 displacement 、 Splicing 、 Conditional operators .

Most operators are related to C The language is similar to . Between operators of the same type , The division operator is associated from right to left , Other operators are left to right associative . Expressions in parentheses take precedence . For example, the following groups of 2 Both are equivalent .

// Right to left Association , The two expressions are equivalent 
A+B-C ;
(A+B）-C ;

// Right to left Association , The two expressions are equivalent , The result is  B、D  or  F
A ? B : C ? D : F ;
A ? B : (C ? D : F) ;

// Right to left Association , The two expressions are not equivalent 
(A ? B : C) ? D : F ;  // result  D  or  F
A ? B : C ? D : F ; // The result is  B、D  or  F

Between different operators , Priorities are different . The following table lists the order of precedence of operators from high to low . When there are no parentheses ,Verilog The expression will be evaluated according to the operator priority . In order to avoid the calculation confusion caused by operator priority , When the priority is uncertain , It is recommended to use parentheses to distinguish expressions .

The operator	Operation symbol	priority
Monocular operations	+ - ! ~	The highest
ride 、 except 、 modulus	* / %
Addition and subtraction	+ -
displacement	<<  >>
Relationship	<  <=  >  >=
Equivalent	==  !=  ===  !===
reduction	& ~&
	^ ~^
	| ~|
Logic	&&
	||
Conditions	?:	The minimum

arithmetic operator

Arithmetic operators include monocular operators and binocular operators .

Binocular operator pairs 2 Operands to perform arithmetic operations , Including multiplication （*）、 except （/）、 Add （+）、 reduce （-）、 Exponentiation （**）、 modulus （%）.

example

reg [3:0]  a, b;
reg [4:0]  c ;
a = 4'b0010 ;
b = 4'b1001 ;
c = a+b;        // The result is c=b'b1011
c = a/b;          // The result is c=4, integer

If one of the operand bits is X, Then the calculation results will all appear X. for example ：

example

b = 4'b100x ;
c = a+b ;       // The result is c=4'bxxxx

When declaring variables , The bit width of the variable should be reasonably declared according to the operator of the variable , Don't let the results overflow . In the above example , additive 2 The bit width of variables is 4bit, Then the bit width of the result register variable is at least 5bit. otherwise , The high bit will be truncated , Result in the loss of the high bit of the result . When multiplying unsigned numbers , The result variable bit width should be 2 The sum of the operands .

example

reg [3:0]        mula ;
reg [1:0]        mulb;
reg [5:0]        res ;
mula = 4'he   ;
mulb = 2'h3   ;
res  = mula * mulb ; // The result is res=6'h2a, The data result has no missing digits

+ and - It can also be used as a monocular operator , Indicates the negativity of operands . This type of operator has the highest priority .

-4  // Negative 4
+3  // Express positive 3

When a negative number indicates , You can add a minus sign directly in front of the decimal number  -, You can also specify the bit width . Because negative numbers are represented by binary complements , Do not refer to the positioning width to represent a negative number , The compiler is converting , The bit width will be allocated automatically , Which leads to unexpected results . for example ：

example

mula = -4'd4 ;
mulb = 2 ;
res = mula * mulb ;      // The calculation result is res=-6'd8, namely res=6'h38, normal
res = mula * (-'d4) ;    //(4 Of 32 The next power -4) * 2, The result is abnormal

Relational operator

Relational operators have greater than （>）, Less than （<）, Greater than or equal to （>=）, Less than or equal to （<=）.

The normal results of relational operators are 2 Kind of , really （1） Or false （0）.

If one of the operands is x or z, Then the result of the relationship expression is x.

example

A = 4 ;
B = 3 ;
X = 3'b1xx ;
   
A > B     // It's true
A <= B    // For false
A >= Z    // by X, Not sure

Equivalent operator

Equivalence operators include logical equality （==）, Logical inequality （!=）, Congruence （===）, Non congruent （!==）.

The normal results of an equivalent operator are 2 Kind of ： It's true （1） Or false （0）.

Logical equality / The inequality operator cannot compare x or z, When the operand contains a x or z, Then the result is an uncertain value .

Congruent comparison , If the bitwise comparison has the same x or z, The return result can also be 1, That is, congruent comparison can be compared x or z. therefore , The result of congruent comparison must not include x. Examples are as follows ：

example

A = 4 ;
B = 8'h04 ;
C = 4'bxxxx ;
D = 4'hx ;
A == B        // It's true
A == (B + 1)  // For false
A == C        // by X, Not sure
A === C       // For false , The return value is 0
C === D       // It's true , The return value is 1

Logical operators

Logical operators mainly include 3 individual ：&&（ Logic and ）, ||（ Logic or ）,!（ Logic is not ）.

The result of the logical operator is 1bit Value ,0 Said the false ,1 Said really ,x Indicates uncertainty .

If an operand is not 0, It is equivalent to logic 1; If an operand is equal to 0, It is equivalent to logic 0. If any of its bits is x or z, It is equivalent to x.

If any operand contains x, The result of logical operator operation is not necessarily x.

The operands of logical operators can be variables , It can also be an expression . for example ：

example

A = 3;
B = 0;
C = 2'b1x ;
   
A && B    //     For false
A || B    //     It's true
! A       //     For false
! B       //     It's true
A && C    //     by X, Not sure
A || C    //     It's true , because A It's true
(A==2) && (! B)  // It's true , At this point, the first operand is the expression

The bitwise operator

Bitwise operators include ： Take the opposite （~）, And （&）, or （|）, Exclusive or （^）, Same as or （~^）.

Bitwise operator pair 2 Each of the operands 1bit Bitwise operation of data .

If 2 The width of the operands is not equal , Then use 0 Extend left to supplement shorter operands .

The negation operator has only one operand , It is for each of the operands 1bit Reverse the data .

The following figure shows the logical rules of bitwise operators .

&( And ）	0	1	x		|( or )	0	1	x
0	0	0	0		0	0	1	x
1	0	1	x		1	1	1	1
x	0	x	x		x	x	1	x

^( Exclusive or )	0	1	x		~^( Same as or )	0	1	x
0	0	1	x		0	1	0	x
1	1	0	x		1	0	1	x
x	x	x	x		x	x	x	x

example

A = 4'b0101 ;
B = 4'b1001 ;
C = 4'bx010 ;
   
~A        //4'b1010
A & B     //4'b0001
A | B     //4'b1101
A^B       //4'b1100
A ~^ B    //4'b0011
B | C     //4'b1011
B&C       //4'bx000

Reduction operator

Reduction operators include ： Reduction and （&）, Reduction and non （~&）, Reduction or （|）, Reduced or non （~|）, Reductive XOR （^）, Reductive congruence or （~^）.

The reduction operator has only one operand , It operates on the vector operand bit by bit , In the end, a 1bit result .

Logical operators 、 The bitwise operator and the reduction operator both use the same symbols to denote , So sometimes it's easy to confuse . The key to distinguishing these operators is to distinguish the number of operands , And the rules of calculation results .

A = 4'b1010 ;
&A ;      // The result is  1 & 0 & 1 & 0 = 1'b0, Can be used to judge variables A Whether all 1
~|A ;     // The result is  ~(1 | 0 | 1 | 0) = 1'b0,  Can be used to judge variables A Whether it is all 0
^A ;      // The result is  1 ^ 0 ^ 1 ^ 0 = 1'b0

Shift operator

Shift operators include shift left （<<）, Move right （>>）, Arithmetic shift left （<<<）, Arithmetic shift right （>>>）.

The shift operator is a binocular operator , The two operands respectively represent the vector signal to be shifted （ To the left of the operator ） And the number of bits moved （ To the right of the operator ）.

Arithmetic shift left and logical shift left , The low position on the right will be filled 0.

When logic moves right , The high position on the left will be filled 0; When arithmetic is shifted to the right , The high bit on the left will be supplemented by the sign bit , To ensure the correctness of the value after data reduction .

example

A = 4'b1100 ;
B = 4'b0010 ;
A = A >> 2 ;        // The result is 4'b0011
A = A << 1;         // The result is 4'b1000
A = A <<< 1 ;       // The result is 4'b1000
C = B + (A>>>2);    // The result is 2 + (-4/4) = 1, 4'b0001

Splicing operators

The splicing operator uses curly braces  {,}  To express , Used to convert multiple operands （ vector ） Splice into new operands （ vector ）, Signals are separated by commas .

The splice operand must specify a bit width , Constant, you also need to specify the bit width . for example ：

example

A = 4'b1010 ;
B = 1'b1 ;
Y1 = {B, A[3:2], A[0], 4'h3 };  // The result is Y1='b1100_0011
Y2 = {4{B}, 3'd4};  // The result is Y2=7'b111_1100
Y3 = {32{1'b0}};  // The result is Y3=32h0, Usually used as the initial value of matching bit width during register initialization

Conditional operators

Conditional expressions have 3 Operators , The structure is described as follows ：

condition_expression ? true_expression : false_expression

When calculating , If condition_expression It's true （ The logical value is 1）, Then the result is true_expression; If condition_expression For false （ The logical value is 0）, Then the result is false_expression.

assign hsel    = (addr[9:8] == 2'b0) ? hsel_p1 : hsel_p2 ;
// When the signal  addr  high  2bit  by  0  when ,hsel  The assignment is  hsel_p1;  otherwise , take  hsel_p2  Assign a value to  hsel.

Actually , The conditional expression is similar to 2 road （ Or multiple ） Selectors , It can be described in if-else Sentence instead .

Of course, conditional operators can also be nested , Complete a multiple choice logic . for example ：

example

assign   hsel = (addr[9:8] == 2'b00) ? hsel_p1 :
                (addr[9:8] == 2'b01) ? hsel_p2 :
                (addr[9:8] == 2'b10) ? hsel_p3 :
                (addr[9:8] == 2'b11) ? hsel_p4 ;