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VHDL编程实验练习题合集
2022-06-12 23:46:00 【鹅毛在路上了】
1.按要求完成相应的功能。
设计 6 位二进制加法器，加法器的频率为 1Hz，进行下载测试，记录测试结果。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
PORT(INCLK: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC_VECTOR(5 DOWNTO 0)); --6位二进制
END CNT6;
ARCHITECTURE ARCH_CNT6 OF CNT6 IS
SIGNAL FP: STD_LOGIC_VECTOR(24 DOWNTO 0);
SIGNAL F: STD_LOGIC;
SIGNAL Q: STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
PROCESS(INCLK)
BEGIN
IF(INCLK'EVENT AND INCLK='1')THEN
IF FP=24999999 THEN --分频1Hz
FP<=(OTHERS=>'0');
F<=not F;
else FP<=FP+1;
end if;
end if;
end process;
process(F)
begin
if (F'event and f='1') then
Q<=Q+1; --硬件连接6个LED
end if;
end process;
OUTPUT<=Q;
end ARCH_CNT6;
2.按要求完成相应的功能。
设计 4 位二进制加法器，加法器的频率为 0.25Hz，进行下载测试，记录测试结果。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4 IS
PORT(INCLK: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --4位二进制
END CNT4;
ARCHITECTURE ARCH_CNT4 OF CNT4 IS
SIGNAL FP: STD_LOGIC_VECTOR(26 DOWNTO 0);
SIGNAL F: STD_LOGIC;
SIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(INCLK)
BEGIN
IF(INCLK'EVENT AND INCLK='1')THEN
IF FP= 99999999 THEN --分频0.25Hz
FP<=(OTHERS=>'0');
F<=not F;
else FP<=FP+1;
end if;
end if;
end process;
process(F)
begin
if (F'event and f='1') then
Q<=Q+1; --硬件连接4个LED
end if;
end process;
OUTPUT<=Q;
end ARCH_CNT4;
3.按要求完成相应的功能。
设计 4 位流水灯程序，流水频率为 1Hz，进行下载测试，记录测试结果。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED1 IS
PORT(INCLK: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --2位二进制表示4种状态
END LED1;
ARCHITECTURE ARCH_LED1 OF LED1 IS
SIGNAL FP: STD_LOGIC_VECTOR(24 DOWNTO 0);
SIGNAL F: STD_LOGIC;
SIGNAL Q: STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
PROCESS(INCLK)
BEGIN
IF(INCLK'EVENT AND INCLK='1')THEN
IF FP= 24999999 THEN --分频1Hz
FP<=(OTHERS=>'0');
F<=not F;
ELSE FP<=FP+1;
END IF;
END IF;
END PROCESS;
PROCESS(F) --Q用作计数
BEGIN
IF (F'event and f='1') then
Q<=Q+1;
END IF;
END PROCESS;
PROCESS(Q) --流水灯进程
BEGIN
CASE Q IS
WHEN "00" => OUTPUT <= "1110";
WHEN "01" => OUTPUT <= "1101";
WHEN "10" => OUTPUT <= "1011";
WHEN "11" => OUTPUT <= "0111";
--WHEN "00" => OUTPUT <= "0111";
--WHEN "01" => OUTPUT <= "1011";
--WHEN "10" => OUTPUT <= "1101";
--WHEN "11" => OUTPUT <= "1110";
END CASE;
END PROCESS;
end ARCH_LED1;
4.按要求完成相应的功能。
设计 4 位流水灯程序，流水频率为 0.25Hz，进行下载测试，记录测试结果。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED2 IS
PORT(INCLK: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --2位二进制表示4种状态
END LED2;
ARCHITECTURE ARCH_LED2 OF LED2 IS
SIGNAL FP: STD_LOGIC_VECTOR(26 DOWNTO 0);
SIGNAL F: STD_LOGIC;
SIGNAL Q: STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
PROCESS(INCLK)
BEGIN
IF(INCLK'EVENT AND INCLK='1')THEN
IF FP= 99999999 THEN --分频0.25Hz
FP<=(OTHERS=>'0');
F<=not F;
ELSE FP<=FP+1;
END IF;
END IF;
END PROCESS;
PROCESS(F) --Q用作计数
BEGIN
IF (F'event and f='1') then
Q<=Q+1;
END IF;
END PROCESS;
PROCESS(Q) --流水灯进程
BEGIN
CASE Q IS
WHEN "00" => OUTPUT <= "1110";
WHEN "01" => OUTPUT <= "1101";
WHEN "10" => OUTPUT <= "1011";
WHEN "11" => OUTPUT <= "0111";
--WHEN "00" => OUTPUT <= "0111";
--WHEN "01" => OUTPUT <= "1011";
--WHEN "10" => OUTPUT <= "1101";
--WHEN "11" => OUTPUT <= "1110";
END CASE;
END PROCESS;
end ARCH_LED2;
5.按要求完成相应的功能。
用文本输入法设计一个 12 归 1 电路，并进行功能测试，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity T12TO1 is
port(finclk:in std_logic;
outputa:out std_logic_vector(7 downto 0);
outputb:out std_logic_vector(7 downto 0));
end T12TO1;
architecture arch_T12TO1 of T12TO1 is
signal sa,sb:std_logic_vector(3 downto 0);
signal f:std_logic;
component fp
port(inclk:in std_logic;
outputa:out std_logic);
end component;
begin
u1:fp port map(finclk,f);
process(f)
begin
if(rising_edge(f)) then
if(sa=2 and sb=1) then
sa<="0001";
sb<="0000";
else
if sa=9 then
sa<="0000";
sb<=sb+1;
else
sa<=sa+1;
end if;
end if;
end if;
end process;
with sa select
outputa<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
with sb select
outputb<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
end architecture arch_T12TO1;
6.按要求完成相应的功能。
用文本输入法设计一个 59 归 0 电路，并进行功能测试，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity T59TO0 is
port(finclk:in std_logic;
outputa:out std_logic_vector(7 downto 0);
outputb:out std_logic_vector(7 downto 0));
end T59TO0;
architecture arch_T59TO0 of T59TO0 is
signal sa,sb:std_logic_vector(3 downto 0);
signal f:std_logic;
component fp
port(inclk:in std_logic;
outputa:out std_logic);
end component;
begin
u1:fp port map(finclk,f);
process(f)
begin
if(rising_edge(f)) then
if(sa=9 and sb=5) then
sa<="0000";
sb<="0000";
else
if sa=9 then
sa<="0000";
sb<=sb+1;
else
sa<=sa+1;
end if;
end if;
end if;
end process;
with sa select
outputa<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
with sb select
outputb<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
end architecture arch_T59TO0;
用文本输入法设计一个 23 归 0 电路，并进行功能测试，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity T23TO0 is
port(finclk:in std_logic;
outputa:out std_logic_vector(7 downto 0);
outputb:out std_logic_vector(7 downto 0));
end T23TO0;
architecture arch_T23TO0 of T23TO0 is
signal sa,sb:std_logic_vector(3 downto 0);
signal f:std_logic;
component fp
port(inclk:in std_logic;
outputa:out std_logic);
end component;
begin
u1:fp port map(finclk,f);
process(f)
begin
if(rising_edge(f)) then
if(sa=3 and sb=2) then
sa<="0000";
sb<="0000";
else
if sa=9 then
sa<="0000";
sb<=sb+1;
else
sa<=sa+1;
end if;
end if;
end if;
end process;
with sa select
outputa<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
with sb select
outputb<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
end architecture arch_T23TO0;
8.按要求完成相应的功能。
用文本输入法设计一个 7 归 4 电路，用一个数码管显示，并进行功能测试，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity T7TO4 is
port(finclk:in std_logic;
outputa:out std_logic_vector(7 downto 0);
outputb:out std_logic_vector(7 downto 0));
end T7TO4;
architecture arch_T7TO4 of T7TO4 is
signal sa,sb:std_logic_vector(3 downto 0);
signal f:std_logic;
component fp
port(inclk:in std_logic;
outputa:out std_logic);
end component;
begin
u1:fp port map(finclk,f);
process(f)
begin
if(rising_edge(f)) then
if(sa=7 and sb=0) then
sa<="0100";
sb<="0000";
else
if sa=9 then
sa<="0000";
sb<=sb+1;
else
sa<=sa+1;
end if;
end if;
end if;
end process;
with sa select
outputa<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
with sb select
outputb<="01100000"when"0001",
"11011010"when"0010",
"11110010"when"0011",
"01100110"when"0100",
"10110110"when"0101",
"10111110"when"0110",
"11100000"when"0111",
"11111110"when"1000",
"11110110"when"1001",
"11101110"when"1010",
"00111110"when"1011",
"10011100"when"1100",
"01111010"when"1101",
"10011110"when"1110",
"10001110"when"1111",
"11111100"when others;
end architecture arch_T7TO4;
9.按要求完成相应的功能，记录测试结果。
用文本输入法设计一个时钟电路，由 4 个动态数码管模拟显示时、分的计时过程。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter9 is
port(inclk: in std_logic;
outseg: out std_logic_vector(7 downto 0); --段选
outbit: out std_logic_vector(3 downto 0)); --位选
end counter9;
Architecture a_counter9 of counter9 is
signal ma,mb,mc,md,me,mf,mseg:std_logic_vector(3 downto 0);
signal lm,hm:std_logic_vector(12 downto 0);
signal fpa,fpb:std_logic;
signal st:std_logic_vector(1 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk='1')then
if lm=1249 then --分频计数
lm<=(others => '0');fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if hm=1249 then
hm<=(others => '0');fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
process(fpb)
begin
if(fpb'event and fpb='1')then
if ma=9 then --分钟个位，59归0
ma<="0000";
if mb=5 then
mb<="0000";
if(mc=2 and md=1)then --12归1小时
mc<="0001";md<="0000";
else
if mc=9 then
md<=md+1;mc<="0000";
else
mc<=mc+1;
end if;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
st<=st+1;
end if;
end process;
process(st)
begin
case st is
when "00"=> --min
mseg<=ma;
outbit<="1110";
when "01"=>
mseg<=mb;
outbit<="1101";
when "10"=> --hour
mseg<=mc;
outbit<="1011";
when "11"=>
mseg<=md;
outbit<="0111";
when others=>
outbit<="1111";
end case;
end process;
with mseg select
outseg<= "01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"00000010" when "1111", --显示g段，用于分割数码管显示
"11111100" when others; --异常状态
end a_counter9;
10.按要求完成相应的功能，记录测试结果。
用文本输入法设计一个时钟电路，由 5 个动态数码管模拟显示时、分的计时过程，时分间用“-”间隔。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter10 is
port(inclk: in std_logic;
outseg: out std_logic_vector(7 downto 0); --段选
outbit: out std_logic_vector(4 downto 0)); --位选
end counter10;
Architecture a_counter10 of counter10 is
signal ma,mb,mc,md,mseg:std_logic_vector(3 downto 0);
signal lm,hm:std_logic_vector(12 downto 0);
signal fpa,fpb:std_logic;
signal st:std_logic_vector(2 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk='1')then
if lm=1249 then --分频计数
lm<=(others => '0');fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if hm=1249 then
hm<=(others => '0');fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
process(fpb)
begin
if(fpb'event and fpb='1')then
if ma=9 then --分钟个位，59归0
ma<="0000";
if mb=5 then
mb<="0000";
if(mc=2 and md=1)then --12归1小时
mc<="0001";md<="0000";
else
if mc=9 then
md<=md+1;mc<="0000";
else
mc<=mc+1;
end if;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
st<=st+1;
end if;
end process;
process(st)
begin
case st is
when "000"=> --min
mseg<=ma;
outbit<="11110";
when "001"=>
mseg<=mb;
outbit<="11101";
when "010"=>
mseg<="1111"; --g段
outbit<="11011";
when "011"=> --hour
mseg<=mc;
outbit<="10111";
when "100"=>
mseg<=md;
outbit<="01111";
when others=>
outbit<="11111";
end case;
end process;
with mseg select
outseg<= "01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"00000010" when "1111", --显示g段，用于分割数码管显示
"11111100" when others; --异常状态
end a_counter10;
11.按要求完成相应的功能，记录测试结果。
用文本输入法设计一个时钟电路，由 6 个动态数码管模拟显示时、分、秒的计时过程。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter11 is
port(inclk: in std_logic;
outseg: out std_logic_vector(7 downto 0); --段选
outbit: out std_logic_vector(5 downto 0)); --位选
end counter11;
Architecture a_counter11 of counter11 is
signal ma,mb,mc,md,me,mf,mseg:std_logic_vector(3 downto 0);
signal lm,hm:std_logic_vector(12 downto 0);
signal fpa,fpb:std_logic;
signal st:std_logic_vector(2 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk='1')then
if lm=1249 then --分频计数
lm<=(others => '0');fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if hm=1249 then
hm<=(others => '0');fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
process(fpb)
begin
if(fpb'event and fpb='1')then
if mf=9 then --分钟个位，59归0
mf<="0000";
if me=5 then
me<="0000";
if ma=9 then --分钟个位，59归0
ma<="0000";
if mb=5 then
mb<="0000";
if(mc=2 and md=1)then --12归1小时
mc<="0001";md<="0000";
else
if mc=9 then
md<=md+1;mc<="0000";
else
mc<=mc+1;
end if;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
end if;
else
me<=me+1;
end if;
else
mf<=mf+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
st<=st+1;
end if;
end process;
process(st)
begin
case st is
when "000"=> --sec
mseg<=mf;
outbit<="111110";
when "001"=>
mseg<=me;
outbit<="111101";
when "010"=>
mseg<=ma; --min
outbit<="111011";
when "011"=>
mseg<=mb;
outbit<="110111";
when "100"=> --hour
mseg<=mc;
outbit<="101111";
when "101"=>
mseg<=md;
outbit<="011111";
when others=>
outbit<="111111";
end case;
end process;
with mseg select
outseg<= "01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"00000010" when "1111", --显示g段，用于分割数码管显示
"11111100" when others; --异常状态
end a_counter11;
12.按要求完成相应的功能，记录测试结果。
用文本输入法设计一个时钟电路，由 8 个动态数码管模拟显示时、分、秒的计时过程，时分秒间用“-”间隔。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(inclk: in std_logic;
outseg: out std_logic_vector(7 downto 0); --段选
outbit: out std_logic_vector(7 downto 0)); --位选
end counter;
Architecture a_counter of counter is
signal ma,mb,mc,md,me,mf,mseg:std_logic_vector(3 downto 0);
signal lm,hm:std_logic_vector(12 downto 0);
signal fpa,fpb:std_logic;
signal st:std_logic_vector(3 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk='1')then
if lm=1249 then --分频计数
lm<=(others => '0');fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if hm=1249 then
hm<=(others => '0');fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
process(fpb)
begin
if(fpb'event and fpb='1')then
if mf=9 then --秒个位，59归0
mf<="0000";
if me=5 then
me<="0000";
if ma=9 then --分钟个位，59归0
ma<="0000";
if mb=5 then
mb<="0000";
if(mc=2 and md=1)then --12归1小时
mc<="0001";md<="0000";
else
if mc=9 then
md<=md+1;mc<="0000";
else
mc<=mc+1;
end if;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
end if;
else
me<=me+1;
end if;
else
mf<=mf+1;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
st<=st+1;
end if;
end process;
process(st)
begin
case st is
when "0000"=>
mseg<=mf; --sec
outbit<="11111110";
when "0001"=>
mseg<=me; --sec
outbit<="11111101";
when "0010"=>
mseg<="1111"; --g
outbit<="11111011";
when "0011"=> --min
mseg<=ma;
outbit<="11110111";
when "0100"=>
mseg<=mb;
outbit<="11101111";
when "0101"=>
mseg<="1111"; --g
outbit<="11011111";
when "0110"=> --hour
mseg<=mc;
outbit<="10111111";
when "0111"=>
mseg<=md;
outbit<="01111111";
when others=>
outbit<="11111111";
end case;
end process;
with mseg select
outseg<= "01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"00000010" when "1111", --显示g段，用于分割数码管显示
"11111100" when others; --异常状态
end a_counter;
13.按要求完成相应的功能。
用文本输入法设计一个 4 位 BCD 码转换电路，并进行下载测试，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bcdconvert4 is
port(ina:in std_logic_vector(3 downto 0);
inclk:in std_logic;
outseg: out std_logic_vector(7 downto 0);
outbit: out std_logic_vector(1 downto 0));
end bcdconvert4;
architecture arch_bcdconvert4 of bcdconvert4 is
signal sina:std_logic_vector(3 downto 0);
signal souta,soutb:std_logic_vector(3 downto 0);
signal ssouta,ssoutb:std_logic_vector(3 downto 0);
signal outa,outc,outb:std_logic_vector(7 downto 0);
signal lm:std_logic_vector(12 downto 0);
signal fpa:std_logic;
signal st:std_logic_vector(1 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk ='1')then
if lm = 4999 then
lm <= (others => '0');fpa<= not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(inclk)
begin
if(inclk'event and inclk ='1')then
if sina="0000"then
ssouta<=souta; souta<="0000";
ssoutb<=soutb; soutb<="0000";
sina<=ina;
else
sina<=sina-1;
if souta=9 then
souta<="0000";
if soutb=9 then
soutb<="0000";
else
soutb<=soutb+1;
end if;
else
souta<=souta+1;
end if;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if st=2 then
st<=(others=>'0');
else
st<=st+1;
end if;
end if;
end process;
process(st)
begin
case st is
when"00"=>
outseg<=outa;
outbit<="10";
when"01"=>
outseg<=outb;
outbit<="01";
when others=>
outbit<="11";
end case;
end process;
with ssouta select
outa <=
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111",
"11111100" when others;
with ssoutb select
outb <=
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111",
"11111100" when others;
end arch_bcdconvert4;
14.按要求完成相应的功能。
用文本输入法设计一个 8 位 BCD 码转换电路，并进行下载测试，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bcdconvert8 is
port(ina:in std_logic_vector(7 downto 0);
inclk:in std_logic;
outseg: out std_logic_vector(7 downto 0);
outbit: out std_logic_vector(2 downto 0));
end bcdconvert8;
architecture arch_bcdconvert8 of bcdconvert8 is
signal sina:std_logic_vector(7 downto 0);
signal souta,soutb,soutc:std_logic_vector(3 downto 0);
signal ssouta,ssoutb,ssoutc:std_logic_vector(3 downto 0);
signal outa,outc,outb:std_logic_vector(7 downto 0);
signal lm:std_logic_vector(12 downto 0);
signal fpa:std_logic;
signal st:std_logic_vector(1 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk ='1')then
if lm = 4999 then
lm <= (others => '0');fpa<= not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(inclk)
begin
if(inclk'event and inclk ='1')then
if sina="00000000"then
ssouta<=souta; souta<="0000";
ssoutb<=soutb; soutb<="0000";
sina<=ina;
else
sina<=sina-1;
if souta=9 then
souta<="0000";
if soutb=9 then
soutb<="0000";
else
soutb<=soutb+1;
end if;
else
souta<=souta+1;
end if;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa='1')then
if st=2 then
st<=(others=>'0');
else
st<=st+1;
end if;
end if;
end process;
process(st)
begin
case st is
when"00"=>
outseg<=outa;
outbit<="110";
when"01"=>
outseg<=outb;
outbit<="101";
when"10"=>
outseg<=outc;
outbit<="011";
when others=>
outbit<="111";
end case;
end process;
with ssouta select
outa <=
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111",
"11111100" when others;
with ssoutb select
outb <=
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111",
"11111100" when others;
with ssoutc select
outc <=
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111",
"11111100" when others;
end arch_bcdconvert8;
15.按要求完成相应的功能。
用文本输入法设计一个 9 位 BCD 码转换电路，并进行下载测试，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test is
port(ina :in std_logic_vector(8 downto 0);
inclk:in std_logic;
outseg:out std_logic_vector(7 downto 0);
outbit:out std_logic_vector(2 downto 0));
end test;
architecture arth_bcdconvert of test is
signal sina:std_logic_vector(8 downto 0);
signal souta,soutb,soutc:std_logic_vector(3 downto 0);
signal ssouta,ssoutb,ssoutc:std_logic_vector(3 downto 0);
signal outa,outb,outc:std_logic_vector(7 downto 0);
signal lm:std_logic_vector(12 downto 0);
signal fpa:std_logic;
signal st:std_logic_vector(1 downto 0);
begin
process(inclk)
begin
if(inclk'event and inclk = '1')then
if lm = 2499 then
lm<=(others=>'0');fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(inclk)
begin
if(inclk'event and inclk = '1')then
if sina = "00000000"then
ssouta<=souta;
souta<="0000";
ssoutb <=soutb;
soutb<="0000";
ssoutc<=soutc;
soutc<="0000";
sina<=ina;
else
sina<=sina-1;
if souta = 9 then
souta<="0000";
if soutb = 9 then
soutb<="0000";
soutc<=soutc+1;
else
soutb <=soutb +1;
end if;
else
souta <=souta+1;
end if;
end if;
end if;
end process;
process(fpa)
begin
if(fpa'event and fpa = '1')then
if st=2 then
st<=(others=>'0');
else
st<= st+1;
end if;
end if;
end process;
process(st)
begin
case st is
when "00"=>
outseg<=outa;
outbit<="110";
when "01"=>
outseg<=outb;
outbit<="101";
when "10"=>
outseg<=outc;
outbit<="011";
when others=>
outbit<="111";
end case;
end process;
WITH ssouta SELECT
outa <=
"01100000"WHEN"0001", --1
"11011010"WHEN"0010", --2
"11110010"WHEN"0011", --3
"01100110"WHEN"0100", --4
"10110110"WHEN"0101", --5
"10111110"WHEN"0110", --6
"11100000"WHEN"0111", --7
"11111110"WHEN"1000", --8
"11110110"WHEN"1001", --9
"11101110"WHEN"1010", --A
"00111110"WHEN"1011", --b
"10011100"WHEN"1100", --C
"01111010"WHEN"1101", --d
"10011110"WHEN"1110", --E
"10001110"WHEN"1111", --F
"11111100"WHEN OTHERS; --0
WITH ssoutb SELECT
outb <=
"01100000"WHEN"0001", --1
"11011010"WHEN"0010",--2
"11110010"WHEN"0011", --3
"01100110"WHEN"0100", --4
"10110110"WHEN"0101", --5
"10111110"WHEN"0110", --6
"11100000"WHEN"0111", --7
"11111110"WHEN"1000", --8
"11110110"WHEN"1001", --9
"11101110"WHEN"1010", --A
"00111110"WHEN"1011", --b
"10011100"WHEN"1100", --C
"01111010"WHEN"1101", --d
"10011110"WHEN"1110", --E
"10001110"WHEN"1111", --F
"11111100"WHEN OTHERS; --0
WITH ssoutc SELECT
outc <=
"01100000"WHEN"0001", --1
"11011010"WHEN"0010",--2
"11110010"WHEN"0011", --3
"01100110"WHEN"0100", --4
"10110110"WHEN"0101", --5
"10111110"WHEN"0110", --6
"11100000"WHEN"0111", --7
"11111110"WHEN"1000", --8
"11110110"WHEN"1001", --9
"11101110"WHEN"1010", --A
"00111110"WHEN"1011", --b
"10011100"WHEN"1100", --C
"01111010"WHEN"1101", --d
"10011110"WHEN"1110", --E
"10001110"WHEN"1111", --F
"11111100"WHEN OTHERS; --0
end arth_bcdconvert;
16.按要求完成相应的功能。
用文本输入法设计一个 4×4 键盘扫描与显示电路，并进行功能测试，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(1 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(1 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(5 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =59999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="01"then
if inkeymap/="11"then
keyout<=chuout&inkeymap;
end if;
chuout<="10";
elsif chuout="10"then
if inkeymap/="11"then
keyout<=chuout & inkeymap;
end if;
chuout<="01";
else
chuout<="01";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "0111"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"3f";
when"10"=> outled <=x"06";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"66";
when"10"=> outled <=x"6d";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"7f";
when"10"=> outled <=x"67";
when others=> outled <=x"00";
end case;
when "1110"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"39";
when"10"=> outled <=x"5e";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
17.按要求完成相应的功能。
用文本输入法设计一个 4×4 键盘扫描与显示电路，要求自上而下、自左而右依次为“0-
F” ，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(3 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(3 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(7 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =109999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="1110"then
if inkeymap/="1111"then
keyout<=chuout&inkeymap;
end if;
chuout<="1101";
elsif chuout="1101"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1011";
elsif chuout="1011"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="0111";
elsif chuout="0111"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1110";
else
chuout<="1110";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "0111"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"3f";
when"1011"=> outled <=x"06";
when"1101"=> outled <=x"5b";
when"1110"=> outled <=x"4f";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"66";
when"1011"=> outled <=x"6d";
when"1101"=> outled <=x"7d";
when"1110"=> outled <=x"07";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"7f";
when"1011"=> outled <=x"67";
when"1101"=> outled <=x"77";
when"1110"=> outled <=x"7c";
when others=> outled <=x"00";
end case;
when "1110"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"39";
when"1011"=> outled <=x"5e";
when"1101"=> outled <=x"79";
when"1110"=> outled <=x"71";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
18.按要求完成相应的功能。
用文本输入法设计一个 4×4 键盘扫描与显示电路，要求自上而下、自右而左依次为“0- F” ，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(3 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(3 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(7 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =109999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="1110"then
if inkeymap/="1111"then
keyout<=chuout&inkeymap;
end if;
chuout<="1101";
elsif chuout="1101"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1011";
elsif chuout="1011"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="0111";
elsif chuout="0111"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1110";
else
chuout<="1110";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "0111"=> --自上而下
case keyout(7 downto 4)is
when"1110"=> outled <=x"3f"; --自右向左
when"1101"=> outled <=x"06";
when"1011"=> outled <=x"5b";
when"0111"=> outled <=x"4f";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"66";
when"1101"=> outled <=x"6d";
when"1011"=> outled <=x"7d";
when"0111"=> outled <=x"07";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"7f";
when"1101"=> outled <=x"67";
when"1011"=> outled <=x"77";
when"0111"=> outled <=x"7c";
when others=> outled <=x"00";
end case;
when "1110"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"39";
when"1101"=> outled <=x"5e";
when"1011"=> outled <=x"79";
when"0111"=> outled <=x"71";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
19.用文本输入法设计一个 4×4 键盘扫描与显示电路，要求自下而上、自左而右依次为“0-
F” ，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(3 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(3 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(7 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =109999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="1110"then
if inkeymap/="1111"then
keyout<=chuout&inkeymap;
end if;
chuout<="1101";
elsif chuout="1101"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1011";
elsif chuout="1011"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="0111";
elsif chuout="0111"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1110";
else
chuout<="1110";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "1110"=> --自下而上
case keyout(7 downto 4)is
when"0111"=> outled <=x"3f"; --自左向右
when"1011"=> outled <=x"06";
when"1101"=> outled <=x"5b";
when"1110"=> outled <=x"4f";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"66";
when"1011"=> outled <=x"6d";
when"1101"=> outled <=x"7d";
when"1110"=> outled <=x"07";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"7f";
when"1011"=> outled <=x"67";
when"1101"=> outled <=x"77";
when"1110"=> outled <=x"7c";
when others=> outled <=x"00";
end case;
when "0111"=>
case keyout(7 downto 4)is
when"0111"=> outled <=x"39";
when"1011"=> outled <=x"5e";
when"1101"=> outled <=x"79";
when"1110"=> outled <=x"71";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
20.按要求完成相应的功能。
用文本输入法设计一个 4×4 键盘扫描与显示电路，要求自下而上、自右而左依次为“0-
F” ，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(3 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(3 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(7 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =109999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="1110"then
if inkeymap/="1111"then
keyout<=chuout&inkeymap;
end if;
chuout<="1101";
elsif chuout="1101"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1011";
elsif chuout="1011"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="0111";
elsif chuout="0111"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1110";
else
chuout<="1110";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "1110"=> --自下而上
case keyout(7 downto 4)is
when"1110"=> outled <=x"3f"; --自右向左
when"1101"=> outled <=x"06";
when"1011"=> outled <=x"5b";
when"0111"=> outled <=x"4f";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"66";
when"1101"=> outled <=x"6d";
when"1011"=> outled <=x"7d";
when"0111"=> outled <=x"07";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"7f";
when"1101"=> outled <=x"67";
when"1011"=> outled <=x"77";
when"0111"=> outled <=x"7c";
when others=> outled <=x"00";
end case;
when "0111"=>
case keyout(7 downto 4)is
when"1110"=> outled <=x"39";
when"1101"=> outled <=x"5e";
when"1011"=> outled <=x"79";
when"0111"=> outled <=x"71";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
21.按要求完成相应的功能。
用文本输入法设计一个 2（扫描码）×4（返回码）键盘扫描与显示电路，并进行功能测试，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(3 downto 0);
outkey: out std_logic_vector(1 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(3 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(3 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(1 downto 0);
signal inkeymap :std_logic_vector(3 downto 0);
signal keyout :std_logic_vector(5 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =59999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="01"then
if inkeymap/="11"then
keyout<=chuout&inkeymap;
end if;
chuout<="10";
elsif chuout="10"then
if inkeymap/="11"then
keyout<=chuout & inkeymap;
end if;
chuout<="01";
else
chuout<="01";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(3 downto 0)is
when "0111"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"3f";
when"10"=> outled <=x"06";
when others=> outled <=x"00";
end case;
when "1011"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"66";
when"10"=> outled <=x"6d";
when others=> outled <=x"00";
end case;
when "1101"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"7f";
when"10"=> outled <=x"67";
when others=> outled <=x"00";
end case;
when "1110"=>
case keyout(5 downto 4)is
when"01"=> outled <=x"39";
when"10"=> outled <=x"5e";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
22.按要求完成相应的功能。
用文本输入法设计一个 4（扫描码）×2（返回码）键盘扫描与显示电路，并进行功能测试，记录测试结果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key2 is
port
(inclk: in std_logic;
inkey: in std_logic_vector(1 downto 0);
outkey: out std_logic_vector(3 downto 0);
led: out std_logic; --weima
outled: out std_logic_vector(7 downto 0)); --duanma
end key2;
architecture art of key2 is
component tinglmove
port(a: in std_logic_vector(1 downto 0);
clk: IN STD_logic;
b: out std_logic_vector(1 downto 0));
end component;
signal keyclk :std_logic_vector(16 downto 0);
signal chuclk :std_logic_vector(2 downto 0);
signal keyclkout,chuclkout:std_logic;
signal chuout :std_logic_vector(3 downto 0);
signal inkeymap :std_logic_vector(1 downto 0);
signal keyout :std_logic_vector(5 downto 0);
begin
led<='0';
u1: tinglmove port map(inkey,keyclkout,inkeymap);
clk_key:process(inclk)
begin
if(inclk'event and inclk='1')then
if keyclk =59999 then
keyclk<=(others=>'0');
keyclkout<=not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu:process(keyclkout)
begin
if(keyclkout'event and keyclkout='1')then
if chuclk = 4 then
chuclk<="000";
chuclkout<= not chuclkout;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out:process(chuclkout)
begin
if(chuclkout'event and chuclkout='1')then
if chuout="1110"then
if inkeymap/="1111"then
keyout<=chuout&inkeymap;
end if;
chuout<="1101";
elsif chuout="1101"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1011";
elsif chuout="1011"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="0111";
elsif chuout="0111"then
if inkeymap/="1111"then
keyout<=chuout & inkeymap;
end if;
chuout<="1110";
else
chuout<="1110";
end if;
end if;
end process clk_chu_out;
outkey<=chuout;
out_led:process(keyout)
begin
case keyout(1 downto 0)is
when "01"=>
case keyout(5 downto 2)is
when"0111"=> outled <=x"3f";
when"1011"=> outled <=x"06";
when"1101"=> outled <=x"5b";
when"1110"=> outled <=x"4f";
when others=> outled <=x"00";
end case;
when "10"=>
case keyout(5 downto 2)is
when"0111"=> outled <=x"66";
when"1011"=> outled <=x"6d";
when"1101"=> outled <=x"7d";
when"1110"=> outled <=x"07";
when others=> outled <=x"00";
end case;
when others=> outled <=x"00";
end case;
end process out_led;
end art;
23.按要求完成相应的功能。
用文本输入法设计一个交通灯程序，主路红灯亮 30 秒，绿灯亮 25 秒，两灯间隔用黄灯间
隔闪烁 5 秒，并用数码管显示倒计时，记录实验现象。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CROSS IS PORT
(INCLK: IN STD_LOGIC;
LED_R_Z:OUT STD_LOGIC;
LED_G_Z:OUT STD_LOGIC;
LED_R_F:OUT STD_LOGIC;
LED_G_F:OUT STD_LOGIC;
outseg: out std_logic_vector(7 downto 0);
outbit: out std_logic_vector(1 downto 0));
END CROSS;
ARCHITECTURE A_CROSS OF CROSS IS
COMPONENT bcdconvert
PORT(ina:in std_logic_vector(7 downto 0);
inclk:in std_logic;
outseg: out std_logic_vector(7 downto 0);
outbit: out std_logic_vector(1 downto 0));
END COMPONENT;
SIGNAL FP:STD_LOGIC_VECTOR(24 DOWNTO 0);
SIGNAL FPA:STD_LOGIC;
SIGNAL CNT:STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE LED_STATE IS (S0,S1,S2,S3);
SIGNAL CS:LED_STATE;
BEGIN
U1:bcdconvert PORT MAP(CNT,INCLK,OUTSEG,OUTBIT);
PROCESS(INCLK)
BEGIN
IF(INCLK'EVENT AND INCLK='1')THEN
IF FP=24999999 THEN
FP<=(OTHERS=>'0');
FPA<=NOT FPA;
ELSE FP<=FP+1;
END IF;
END IF;
END PROCESS;
PROCESS(FPA)
BEGIN
IF RISING_EDGE(FPA)THEN
CASE CS IS
WHEN S0=>
IF CNT=0 THEN --若计数值为0
CNT<=X"07"; --00001001,也就是10进制的5
CS<=S1; --进入S1状态
ELSE CNT<=CNT-1;
CS<=S0; --若计数未结束，继续返回S0计数
END IF;
WHEN S1=>
IF CNT=0 THEN --若计数值为0
CNT<=X"3B"; --00111011,也就是10进制的59
CS<=S2; --进入S2状态
ELSE CNT<=CNT-1;
CS<=S1; --若计数未结束，继续返回S1计数
END IF;
WHEN S2=>
IF CNT=0 THEN
CNT<=X"07";
CS<=S3;
ELSE CNT<=CNT-1;
CS<=S2;
END IF;
WHEN S3=>
IF CNT=0 THEN
CNT<=X"3B";
CS<=S0;
ELSE CNT<=CNT-1;
CS<=S3;
END IF;
WHEN OTHERS=>
CNT<=(OTHERS=>'0');
CS<=S0;
END CASE;
END IF;
END PROCESS;
LED_R_Z<='0'WHEN CS=S0 ELSE --主路红灯
'0' WHEN(CS=S1 OR CS=S3) AND FPA='1' ELSE
'1';
LED_G_Z<='0'WHEN CS=S2 ELSE --主路绿灯
'0' WHEN(CS=S1 OR CS=S3) AND FPA='1' ELSE
'1';
LED_R_F<='0'WHEN CS=S2 ELSE --辅路
'0' WHEN(CS=S1 OR CS=S3) AND FPA='1' ELSE
'1';
LED_G_F<='0'WHEN CS=S0 ELSE
'0' WHEN(CS=S1 OR CS=S3) AND FPA='1' ELSE
'1';
END A_CROSS;
24.按要求完成相应的功能。
用文本输入法设计一个交通灯程序，主路红灯亮 59 秒，绿灯亮 59 秒，两灯间隔用黄灯间
隔闪烁 7 秒，并用数码管显示倒计时，记录实验现象。
IF CNT=0 THEN --若计数值为0
CNT<=X"06"; -- CS<=S1; --进入S1状态
ELSE CNT<=CNT-1;
CS<=S0; --若计数未结束，继续返回S0计数
END IF;
WHEN S1=>
IF CNT=0 THEN --若计数值为0
CNT<=X"3a"; -- CS<=S2; --进入S2状态
ELSE CNT<=CNT-1;
CS<=S1; --若计数未结束，继续返回S1计数
END IF;
WHEN S2=>
IF CNT=0 THEN
CNT<=X"06";
CS<=S3;
ELSE CNT<=CNT-1;
CS<=S2;
END IF;
WHEN S3=>
IF CNT=0 THEN
CNT<=X"3a";
CS<=S0;
ELSE CNT<=CNT-1;
CS<=S3;
END IF;
WHEN OTHERS=>
CNT<=(OTHERS=>'0');
CS<=S0;
END CASE;
END IF;
END PROCESS;
25.用文本输入法设计一个交通灯程序，主路红灯亮 10 秒，绿灯亮 27 秒，两灯间隔用黄灯间
隔闪烁 8 秒，并用数码管显示倒计时，记录实验现象。
IF CNT=0 THEN --若计数值为0
CNT<=X"07"; --
CS<=S1; --进入S1状态
ELSE CNT<=CNT-1;
CS<=S0; --若计数未结束，继续返回S0计数
END IF;
WHEN S1=>
IF CNT=0 THEN --若计数值为0
CNT<=X"1a"; -- CS<=S2; --进入S2状态
ELSE CNT<=CNT-1;
CS<=S1; --若计数未结束，继续返回S1计数
END IF;
WHEN S2=>
IF CNT=0 THEN
CNT<=X"07";
CS<=S3;
ELSE CNT<=CNT-1;
CS<=S2;
END IF;
WHEN S3=>
IF CNT=0 THEN
CNT<=X"09";
CS<=S0;
ELSE CNT<=CNT-1;
CS<=S3;
END IF;
WHEN OTHERS=>
CNT<=(OTHERS=>'0');
CS<=S0;
END CASE;
END IF;
END PROCESS;
26.按要求完成相应的功能。
用文本输入法设计一个交通灯程序，主路红灯亮 40 秒，绿灯亮 45 秒，两灯间隔用黄灯间
隔闪烁 5 秒，并用数码管显示倒计时，记录实验现象。
IF RISING_EDGE(FPA)THEN
CASE CS IS
WHEN S0=>
IF CNT=0 THEN --若计数值为0
CNT<=X"04"; – CS<=S1; --进入S1状态
ELSE CNT<=CNT-1;
CS<=S0; --若计数未结束，继续返回S0计数
END IF;
WHEN S1=>
IF CNT=0 THEN --若计数值为0
CNT<=X"2c"; –
CS<=S2; --进入S2状态
ELSE CNT<=CNT-1;
CS<=S1; --若计数未结束，继续返回S1计数
END IF;
WHEN S2=>
IF CNT=0 THEN
CNT<=X"04";
CS<=S3;
ELSE CNT<=CNT-1;
CS<=S2;
END IF;
WHEN S3=>
IF CNT=0 THEN
CNT<=X"27";
CS<=S0;
ELSE CNT<=CNT-1;
CS<=S3;
END IF;
WHEN OTHERS=>
CNT<=(OTHERS=>‘0’);
CS<=S0;
END CASE;
END IF;
END PROCESS;
27.仿真验证
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(CLK,RST,EN,LOAD:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END ENTITY CNT10;
ARCHITECTURE BHV OF CNT10 IS
BEGIN
PROCESS(CLK,RST,EN,LOAD)
VARIABLE Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RST='0'THEN
Q:=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1'THEN
IF EN='1'THEN
IF(LOAD='0')THEN
Q:= DATA;
ELSE
IF Q < 9 THEN
Q:=Q+1;
ELSE Q:=(OTHERS=>'0');
END IF;
END IF;
END IF;
END IF;
IF Q="1001"THEN
COUT<='1';
ELSE COUT<='0';
END IF;
DOUT<=Q;
END PROCESS;
END ARCHITECTURE BHV;
激励：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TEST IS END TEST;
ARCHITECTURE behaviour OF TEST IS
COMPONENT CNT10
PORT(CLK:IN STD_LOGIC;
RST:IN STD_LOGIC;
EN:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END COMPONENT;
SIGNAL CLK:STD_LOGIC:='0';
SIGNAL RST:STD_LOGIC:='1';
SIGNAL EN:STD_LOGIC:='0';
SIGNAL LOAD:STD_LOGIC:='1';
SIGNAL DATA:STD_LOGIC_VECTOR(3 DOWNTO 0):=(OTHERS=>'0');
SIGNAL DOUT:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUT:STD_LOGIC;
CONSTANT CLK_PERIOD:TIME:=50 ns;
BEGIN
UUT:CNT10 PORT MAP(CLK=>CLK,
RST=>RST,
EN=>EN,
LOAD=>LOAD,
DATA=>DATA,
DOUT=>DOUT,
COUT=>COUT);
CLK_PROCESS:PROCESS
BEGIN
CLK<='0';
WAIT FOR CLK_PERIOD/2;
CLK<='1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
PROCESS
BEGIN
RST<='1';
WAIT FOR 110 NS;
RST<='0';
WAIT FOR 110 NS;
RST<='1';
WAIT;
END PROCESS;
EN<='0','1'AFTER 40 NS;
LOAD<='1','0'AFTER 910 NS,'1'AFTER 940 NS;
DATA<="0100","0110" AFTER 400 NS,"0111" AFTER 700 NS,"0100" AFTER 1000 NS;
END;
28.激励：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TEST IS
END TEST;
ARCHITECTURE BCHAVIOR OF TEST IS
COMPONENT DFF1
port(clk,d: in std_logic;
q:out std_logic);
END COMPONENT;
SIGNAL CLK: STD_LOGIC:='0';
SIGNAL d:STD_LOGIC:='0';
signal q:std_LOGIC;
CONSTANT CLK_PERIOD:TIME:=50 ns;
BEGIN
UUT:DFF1 PORT MAP(CLK=>CLK,
d=>d,
q=>q);
CLK_PROCESS:PROCESS
BEGIN
CLK<='0';
WAIT FOR CLK_PERIOD/2;
CLK<='1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
d<='0','1' after 30 ns,'0' after 60 ns,'1' after 72 ns,
'0' after 80 ns,'1' after 140 ns,'0' after 180 ns;
END BCHAVIOR;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp IS
PORT(clk_in:in std_logic;
clk_1k:out std_logic);
END ENTITY fp;
ARCHITECTURE BHV OF fp IS
signal cnt_1k:integer range 0 to 24999;
BEGIN
PROCESS(clk_in)
BEGIN
IF (clk_in'event and clk_in='1')then
if cnt_1k=24999 then
cnt_1k<=0;
else
cnt_1k<=cnt_1k+1;
END IF;
END IF;
end process;
process(clk_in)
begin
if (clk_in'event and clk_in='1')then
if cnt_1k>12499 then
clk_1k<='1';
else
clk_1k<='0';
end if;
end if;
END PROCESS;
END ARCHITECTURE BHV;
激励：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TEST IS
END TEST;
ARCHITECTURE BCHAVIOR OF TEST IS
COMPONENT fp
port(clk_in: in std_logic;
clk_1k:out std_logic);
END COMPONENT;
SIGNAL clk_in: STD_LOGIC:='0';
signal clk_1k: STD_LOGIC:='0';
CONSTANT CLK_PERIOD:TIME:=40 ns;
BEGIN
UUT:fp PORT MAP(clk_in=>clk_in,
clk_1k=>clk_1k);
CLK_PROCESS:PROCESS
BEGIN
clk_in<='0';
WAIT FOR CLK_PERIOD/2;
clk_in<='1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
END BCHAVIOR;
.vhd脚本，工程附件:
完整工程文件下载链接
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