[Verilog digital system design (Xia Yuwen) 3 ----- basic concepts of Verilog syntax 1]

summary

Verilog HDL It is a language used in digital system design . use Verilog HDL The circuit design described is the design of the circuit Verilog HDL Model , Also known as modules .Verilog HDL It is not only a language of behavior description, but also a language of structure description . That is to say , No matter the module that describes the functional behavior of the circuit or the module that describes the interconnection of components or larger components, it can be used Verilog Language to build circuit model . If it is written according to certain rules and styles , Functional behavior modules can be automatically converted into gate level interconnected structural modules through tools .Verilog Models can be different levels of abstraction of actual circuits .

Model type

The levels of abstraction and their corresponding model types are as follows 5 Kind of ：

(1) The system level (system-level)： The high-level structure provided by language can realize the model of the external performance of the module to be designed .
(2） Algorithm level (algorithm-level)： The high-level structure provided by language can realize the model of algorithm operation .
(3) RTL level (registertransfer level)： Describe the flow of data between registers and how to handle 、 Models that control the flow of these data .
The above three belong to behavior description , Only RTL Level has a clear corresponding relationship with logic circuit .
(4) Gate level (gate-level)： A model that describes logic gates and the connections between them . There is a definite connection with the logic circuit , above 4 A digital system design engineer must master .
(5） Switch level (switch-level)： A model describing the transistor and storage node in the device and the connection between them .

The integrity of a complex circuit system Verilog HDL The model is made up of several Verilog HDL modular , each A module can be composed of several sub modules . Some of the modules need to be integrated into specific circuits , Some modules are only existing circuits or excitation signal sources that interact with the modules designed by users . utilize VerilogHDL This function provided by language structure can construct a clear hierarchical structure between modules , To describe the extremely complex large-scale design , And the design of the logic circuit is strictly verified .

Behavior description language has functions

Verilog HDL Behavior description language is a kind of structured and procedural language , Its syntax structure is very suitable for algorithm level and RTL Level model design . This behavior description language has the following functions ：

1. A program structure that describes sequential or parallel execution ;
2. Delay expressions or event expressions are used to explicitly control the start time of a process ;
3. Activate or stop actions in other processes are triggered by named Events ;
4. Provide conditions such as if-else,case Equal loop program structure ;
5. Provides tasks with parameters and non-zero duration (task) Program structure ;
6. Provides a function structure that defines new operators (function);
7. Provides arithmetic operators for building expressions 、 Logical operators 、 An operator ;
8. Verilog HDL As a structured language, language is very suitable for gate level and switch level model design .

Because of its structural characteristics, it has the following functions ：

1. It provides a complete set of primitives that represent the basic elements of combinatorial logic (primitive);
2. Provides two-way access （ Bus ） And the primitive of resistance device ;
3. Can establish MOS Dynamic models of charge sharing and charge decay in devices .
4.Verilog HDL The constructive statements of can accurately model the signal . This is because in the Verilog HDL in , Primitives for delay and output strength are provided to build a highly accurate signal model . Signal values can have different strengths , The influence of uncertain conditions can be reduced by setting a wide range of fuzzy values .

Summary

(1) Verilog HDL The program is made up of modules . The content of each module is located in module and endmod­ule Between two statements . Each module implements a specific function .
(2) Modules can be nested hierarchically . Because of that , Only in this way can the large digital circuit design be divided into different small modules to achieve specific functions .
(3) If each module can be integrated , Then their function descriptions can be transformed into the most basic logical unit descriptions through the synthesis tools , Finally, you can use An upper module connects these modules through instance references , Integrate them into a large logical system .
(4) Verilog Modules can be divided into two types ： One is to make the module finally generate the structure of the circuit , The other is just to test whether the logic function of the designed circuit is correct .
(5) Each module needs to define the port , And explain the input 、 outlet , Then describe the function of the module .
(6) Verilog HDL The writing format of the program is free , You can write several statements on a line , A statement can also be divided into multiple lines .
(7) except endmodule Out of statement , There must be a semicolon at the end of each statement and data definition .
(8) It can be used ／ ＊ …… ＊ ／ and ／／…… Yes Verilog HDL Comment on any part of the program . A good 、 All useful source programs should be annotated as necessary , To enhance the readability and maintainability of the program .