Write your own CPU Chapter 11 - learning notes

Chapter 11 ： Implementation of exception related instructions

This chapter is to realize the teaching version OpenMIPS The last step of the processor , Will implement exception related instructions .

11.1MIPS32 Exception types defined in the schema

stay MIPS32 Architecture , There are some events to shorten the normal execution process of the program , These times have interruption traps 、 System calls and any other conditions that can interrupt the normal execution process of the program , Collectively referred to as exceptions .

 11.2 Precise anomaly

stay MIPS32 I often read “ Precise anomaly ” This term ,OpenMIPS The implementation blueprint of is also designed to achieve precise exceptions , This section will introduce the related concepts of precise exceptions .

When an exception occurs , The sequential execution of the system will be interrupted , At this time, there are several instructions in different stages of the pipeline , The processor will move to the exception handling agenda , After exception handling, return to the original program to continue execution , Because you don't want the exception handling routine to destroy the normal execution of the original program , So when an exception occurs , Unfinished instructions on the pipeline , You must remember which stage of the assembly line it is in , So that execution can be resumed after exception handling , This is the precise anomaly .

For a processor that implements precise exceptions , When an exception occurs , There will be an instruction interrupted by an exception , Called abnormal victims , It can also be called the instruction with exception , All the instructions preceding this instruction must be executed to the last stage of the pipeline , That is, the normal execution is completed , However, the instruction and the instructions after the instruction must be cancelled , It's like it's never been implemented . In order to achieve precise exception , The order in which exceptions occur must be the same as the order of instructions , On non pipelined processors , This is obvious , But for processors with pipelines , It will be a little complicated . On the pipeline processor , Exceptions occur at different stages of the pipeline , Bring potential problems .

In pipelined processors , The order in which exceptions occur is not necessarily the same as the order of instructions . To avoid this , Exceptions that occur first are not handled immediately , The exception event is simply marked , And continue to run the pipeline . In most processors , Will design a special assembly line stage , Dedicated to handling exceptions . If an abnormal event of an instruction tampers with this stage of the material pipeline , Then exception handling will be performed , And the abnormal events of the instructions currently in the rest of the pipeline will be ignored .

11.3 Exception handling

 

 

 11.4 Introduction to exception related instructions

11.4.1 Self trapping instruction

    Self trapping instruction yes 12 strip , According to whether the instruction contains an immediate number 、 It can be divided into two categories

1. Self trapping instructions that do not contain immediate numbers

 

 

2. A self trapping instruction containing an immediate number  

 

 11.4.2 System call instructions syscall

 11.4.3 Exception return instruction eret

 11.5 Implementation idea of exception handling

 11.5.1 Realize the idea

OpenMIPS The implementation idea of exception handling is ： Collect exception information at all stages of the pipeline , And pass it to the pipeline memory access stage , Handle exception information uniformly in the storage access stage . The exception information to be collected at each stage of the pipeline is as follows .

-- Judge whether there is any system call exception in the pipeline decoding stage , Whether it is a return instruction 、 Invalid instructions .

-- Judge whether there is self trapping exception in the pipeline execution stage 、 Overflow exception

-- Check whether there is an interrupt in the pipeline memory access stage .

 11.5.2 Modify the data flow diagram

An exception judgment module is added in the memory access stage , The main function is based on decoding 、 Information delivered during execution , as well as CP0 The value of the register in , Determine whether to handle exceptions , If you want to handle exceptions , Then give a new instruction address according to the exception type and enter PC.

 11.5.3 Modify the system structure

Add some interfaces .

 11.6 modify OpenMIPS To achieve exception handling

11.6.1 Modify the retrieval stage

1. modify PC modular

 2. modify IF/ID modular

 

 11.6.2 Modify the decoding stage