Analysis of critical path

Critical path analysis

Critical path usually refers to the path in synchronous logic circuit , The path with the greatest delay in combinational logic （ Here I think we need to add the delay of wiring ）, In other words, the critical path is the timing path that has a decisive impact on the design .

Timing optimization of critical path , It can directly improve the design performance . For synchronization logic , Common timing optimization methods include Pipeline、Retiming、 Logical replication 、 Add / Multiplication tree 、 The key signal moves back 、 Eliminate priority and other solutions .

Static timing analysis can find out the critical path of logic circuit . By viewing the static timing analysis report , The critical path can be determined .

1、 Insert register in combinational logic （ Insert pipeline ）
The delay of combinational logic is too long , Will become a critical path , At this time, you can consider inserting additional registers on this path , This method is also called insert pipeline , It is often used in the design of high flow , Because the clock cycle delay increased by inserting additional registers in this design will not violate the specification requirements of the whole design , Thus, the overall functional realization of the design will not be affected , That is to say, the additional inserted registers improve the timing performance of the design while keeping the throughput unchanged . Of course , It will inevitably lead to the addition of part of the area .

When inserting a register , To select an appropriate position in combinatorial logic for insertion , The delay of several small combinational logic blocks divided after inserting the register is basically the same .

It is equivalent to adding register first as shown in the figure below , Then retime the register Retiming.