Adder - Notes

adder

• An adder is a unit that performs the addition function , It has two or three data input ports and two output ports .
• For binary addition operation , Such as 0+0=0,0+1=1,1+1=0, Carry is 1.
• Depending on the number of input ports , Adders are divided into half adders and full adders .

Half adder

• Two input ports , Addend and addend ; Two output ports , Carry and result .
• Common symbols
  
• Logical expression $$F=A\cdot \bar{B}+B\cdot \bar{A}=A\oplus B$$$$Count=A\cdot B$$
• Corresponding truth table
  
• You can find ,$F$ And $A.B$ The relation of is XOR gate ,$Count$ And $A.B$ The relationship between and gate . Therefore, a semi adder can be composed of an XOR gate and an and gate .
  
• Verilog describe

  module half_adder(
  	input	A,
  	input 	B,
  
  	output	F,
  	output Cout
  );
  
  assign F = A ^ B;
  assign Cout = A & B;
  
  endmodule
  

• RTL View
  

Full adder

• On the basis of half adder , Consider the carry of low order operations , So the full adder has three input ports .
  

• Logical expression $$F=A\oplus B\oplus Cin$$$$Cout=A\cdot B+Cin(A\oplus B)$$

• Corresponding truth table
  

• Verilog grammar

  module full_adder(
  	input A,
  	input B,
  	input Cin,
  	
  	output F,
  	output Cout
  );
  
  assign F = A^B^Cin;
  assign Cout = A&B|(Cin&(A^B));
  
  endmodule
  

• RTL View
  

• Another method is to realize full adder , Using two half adders
  

• Since the full adder takes into account the carry of the low order operation , Thus, we can easily add multi bit data by cascading multiple full adders , Such as 8 Bit data
  

• This cascade method is also called traveling wave carry adder , If there is carry , Like a ripple from low to high . This adder , Because each full adder needs to wait for the carry output of its previous full adder to complete the calculation , So it takes a long time 、 Low efficiency . In order to improve the time efficiency of addition , Carry select adder and carry ahead adder are introduced .

• HDLBits There is a question about adder above ： Give a 16 Bit adder add16, To design a 32 Bit adders .
  

• This 16 Bit adders , It can be formed by cascading traveling wave carry , Its internal structure can be free from entanglement , On how to form 32 Bit adder for understanding .

• Verilog Realization

  module top_module(
  	input	[31:0] a,
  	input	[31:0] b,
  	output	[31:0] sum  
  ):
  
  //  Define the internal connection line 
  wire [15:0] a_1, a_2;
  wire [15:0] b_1, b_2;
  wire [15:0] sum_1, sum_2;
  wire cin_1, cin_2, cout_1;	//  Be careful , Here you can see that the following carry has no output , therefore , Can not define .
  
  //  Connect the cable to the port data 
  assign cin_1 = 0;
  assign a_1 = a[15:0];
  assign a_2 = a[31:16];
  assign b_1 = b[15:0];
  assign b_2 = b[31:16];
  assign sum = {
        sum_2,sum_1};
  
  //  call add16 modular 
  add16 add16_inst_1(.a(a_1),.b(b_1),.cin(cin_1),.cout(cout_1));
  add16 add16_inst_2(.a(a_2),.b(b_2),.cin(cin_2));
  
  endmodule
  

• As mentioned earlier , For addition of multi bit bus data , If traveling wave carry is used , It has a long carry chain and key path , Time consuming , Low efficiency . Therefore, several adders based on the carry derivation of traveling wave are introduced .

Carry select adder

• I have learned about multiplexers , Can multiplexers be added to improve the efficiency of traveling wave carry ？ Take the above as an example , Give a 16 Bit adder add16, To design a 32 Bit adders .
• By means of carry selection , The block diagram is as follows
  
• Use 3 individual 16 Bit adders ： Build two high 16 Bit adders , A carry to 0, A carry to 1. Through low 16 The carry signal of the bit adder is used to select which adder value to output .
• Verilog Realization
  
• Simulation results
  
• Advantages and disadvantages ：
  • High and low bits can be operated at the same time , Reduce time ;
  • Large circuit area （ Pictured above , Use more than one adder and selector ）;