FPGA state machine

One 、 State machine implementation

1. State machine ： Implement a test process , This process includes starting the preparation state 、 Start the test 、 Stop test 、 Query test results 、 Display test results 、 After the test, return to initialization 6 Status ; Use time to control the process ,90 Complete the process in seconds

2. Describe the state jump time

   • State machine state
     • s0： Ready to go
     • s1： Start state
     • s2： Stop state
     • s3： Query test results
     • s4： Display test results
     • s5： Return to the initial state after the test
   • Staged jump
     • s0 -> s1 The first 1s Jump to s1
     • s1 -> s2 The first 25s Jump to s2
     • s2 -> s3 The first 55s Jump to s3
     • s3 -> s4 The first 60s Jump to s4
     • s4 -> s5 The first 75s Jump to s5
     • s5 -> s0 The first 90s Jump back to the initial state

3. coded .

module fsm(
	input clk,
	input rst_n,
	output result
);
reg[5:0] state;
reg[27:0] ctn;
parameter max_time=28'd49_999_999;
wire[63:0] timer;
parameter s0 = 6'b100000;
parameter s1 = 6'b010000;
parameter s2 = 6'b001000;
parameter s3 = 6'b000100;
parameter s4 = 6'b000010;
parameter s5 = 6'b000001;

// Counter 
[email protected](posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		ctn <= 28'd0;
	end
	else if(ctn == max_time)begin
		ctn <= 28'd0;
	end
	else ctn <= ctn +1'b1;
end 
always @(posedge clk or negedge rst_n)begin
	if(rst_n)begin
		state <= s0;
	end	
	else
		case(state)
			s0:begin
				if(timer == 1)
					state <= s1;
				else state <= s0;			
			end
			s1:begin
				if(timer == 25)
					state <= s2;
				else state <= state;
			end
			s2:begin
				if(timer == 55)
					state <= s3;
				else state <= state;
			end
			s3:begin
				if(timer == 60)
					state <= s4;
				else state <= state;
			end
			s4:begin
				if(timer == 75)
					state <= s5;
				else state <= state;
			end
			s5:begin
				if(timer == 90)
					state <= s0;
				else state <= state;
			end
			default:sr=state <= s0;	
		endcase
end
endmodule 

Two 、 testing 10010 strand

1. Draw a picture that can detect 10010 State diagram of string
   
2. verilog Programming to realize

module Ce_Top(
	input clk,
	input rst_n,
	input data,
	output result
);
reg result_r;
reg[4:0] state;
parameter IDLE = 5'b10000;
parameter S1   = 5'b01000;
parameter S10  = 5'b00100;
parameter S100 = 5'b00010;
parameter S1001= 5'b00001;
[email protected](posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		state <= IDLE;
		result_r <= 1'b0;
	end	
	else	
		case(state)		
		IDLE: begin
			if(data==0)begin
				state <= IDLE;
				result_r <= 0;
			end	
			else begin
				state <= S1;
				result_r <= 0;
			end
		end
		S1:begin		
			if(data ==0)begin
				state <= S10;
				result_r <= 0;
			end			
			else begin
				state <=S1;
				result_r <= 0;
			end
		end
		S10:begin	
			if(data ==0)begin
				state <= S100;
				result_r <= 0;
			end			
			else begin
				state <=S1;
				result_r <= 0;
			end
		end		
		S100:begin
			if(data==0)begin		
				state <= IDLE;
				result_r <= 0;
			end			
			else begin
				state <= S1001;
				result_r <= 0;
			end
		end		
		S1001:begin
			if(data==0)begin		
				state <= IDLE;
				result_r <= 1;
			end
			else begin
				state <= S1;
				result_r <= 0;
			end
		end
		default: state <= 5'bx;
		endcase
end
assign result =result_r;
endmodule 

3、 ... and 、 summary

The main experiment jumps the state of the experiment through the state machine , Enter different logical sequences , In the code is online, only ideas are written , No board verification test .