[Verilog quick start of Niuke online question brushing series] ~ one out of four multiplexer

0. Preface

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1. One out of four multiplexer

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1.1 Title Description

Make a one out of four multiplexer , The output is required to be defined as the wire network type .

1.1.1 State transition

d0 11
d1 10
d2 01
d3 00

1.1.2 Signal schematic diagram

1.1.3 Input description

Input signal d1,d2,d3,d4 sel
type wire

1.1.4 Output description

The output signal mux_out
type wire

1.2 Their thinking

First , Yes 5 Input signals , among sel Control which data output is , It's simple , You can see by looking at the waveform , Don't talk much , Go straight to the code ！！！

1.3 Code implementation

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
//*************code***********//
    reg [1:0] mux_out_temp;
    always @ (*) begin
        case (sel)
            2'b00 : mux_out_temp = d3;
            2'b01 : mux_out_temp = d2;
            2'b10 : mux_out_temp = d1;
            2'b11 : mux_out_temp = d0;
            default : mux_out_temp = d3;
        endcase
    end

    assign mux_out = mux_out_temp;
//*************code***********//
endmodule

1.3.1 Code instructions

Q1： Why define a reg Type of 2 Bit variables ？
A： because always The assignment statement in the block must be reg Type ,wire Type is not allowed ,wire It's like a thread , and reg It is equivalent to a register .

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