UVM RAL model and built-in seq

There are two major challenges in system design: reducing the size of technology nodes and time to market (TTM).In order to adapt to the fierce market competition, most systems are designed in a generic way, which means that the same design can be implemented in different application ways through different configurations.The higher the number of configurations, the higher the number of registers in the design.On top of that, due to the massive demand for data storage in the current market, storage sizes are also getting larger.In order to access and verify large numbers of registers and huge storage, some innovative methods are required.Therefore, UVM provides a base class library for register management and access, called UVM RAL (Register Abstraction Layer).

As the name suggests, UVM RAL is a high-level object-oriented abstraction layer for accessing design registers.The RAL model mimics the design register, and the entire model is fully configurable.Due to its abstract behavior, the RAL model can be easily migrated from the module level to the system level.

This article provides relevant content about the different levels of UVM RAL, including: how to use the same RAL model for multiple interfaces, the storage implementation inside the RAL model and its access methods, the information of the predictor model and the operation according to itpredict register values, etc.It also has a list of ready-made UVM register sequences.Simply by configuring these sequences, the user can access and verify the functionality of all design registers and stores.

Introduction:

The first step in the verification of any design is its register verification, which checks the accessibility of the registers and their functionality.To perform this register verification, it is not necessary to use the UVM RAL model, but when verifying without it, the user must pay attention to the properties and reset values ​​of each register.Likewise, the user must ensure that each register field is validated with all possible values.Performing these checks manually across the entire register range is a time-consuming task, so using the UVM RAL model is a very efficient approach.

UVM RAL is a model for designing internal registers.To access these design registers, UVM RAL provides ready-made base classes and APIs.Some features of the RAL model include:

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