Solve the error that the simulation output is STX under the frequency division module Modelsim

The following is a uart A routine of , Take this program for example , stay modelsim The output frequency division signal below is stx type , That is, the uncertainty signal , Let's analyze the reasons ：

module uart_clkdiv(clk, rst_n, clkout);

input clk;
input rst_n;
output clkout;

reg clkout;
reg [15:0] cnt;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n) 
    begin
        cnt <= 16'b0;
        clkout <= 1'b0;
    end
    else if(cnt == 16'd1)//pc communication set 13
    begin
        clkout <= 1'b1;
        cnt <= cnt + 16'd1;
    end
    else if(cnt == 16'd3)//pc communication set 26
    begin
        clkout <= 1'b0;
        cnt <= 16'd0;
    end
    else
    begin
        cnt <= cnt + 16'd1;
    end
end

endmodule

The green part is the changed code . The reason for the error is that there is no reset signal to make the variables cnt clkout Generate an initial value , It causes the output to be uncertain . During the simulation testbench In, the reset signal should be reset by pulling down several clock cycles . Therefore, the initial value of each variable needs to be clearly specified during simulation , Prevent uncertain signals .