How to become a senior digital IC Design Engineer (1-4) Verilog coding syntax: expression

One 、 Define expressions

         Take the function definition of advanced mathematics as an example ,Verilog HDL The expression is defined as follows ：

result = operator(operand)

         here ,operand It's input. （ The independent variables ）x,result It is output. （ The dependent variable ）y,operator It's the circuit （ The mapping relationship ）f, By entering operators and data , You can determine the unique output data . As shown below ：

assign result = dina +  dinb;        // arithmetic operator 
assign reslut = dina >  dinb;        // Comparison operator 
assign reslut = dina && dinb;        // Logical operators 
assign reslut = dina &  dinb;        // Bit operators 
assign reslut = dina >> dinb;        // Shift operator 
assign reslut = sel  ?  dinb : dina; // Conditional operators 
assign reslut = {dina,  dinb};       // Join operators 

         It is worth noting that , Operators have priority characteristics , Brackets are recommended in place of their priority ！