Multiplier design (pipeline) Verilog code

One 、 Preface

         Commonly used multiplier design , Generally, a cycle can only be accumulated once , So it takes time to multiply the bit width , If you need a cycle to produce results, you need pipelining .

Two 、 principle

        The variable is saved after each execution of multiplication , Convenient for streamline operation .

3、 ... and 、verilog code

Single accumulation design

module    mult_cell
    #(parameter N=4,
      parameter M=4)
    (
      input                     clk,
      input                     rstn,
      input                     en,
      input [M+N-1:0]           mult1,      // Multiplier
      input [M-1:0]             mult2,      // The multiplier
      input [M+N-1:0]           mult1_acci, // Last cumulative result

      output reg [M+N-1:0]      mult1_o,     // Save the value after the multiplicand shift
      output reg [M-1:0]        mult2_shift, // Save value after multiplier shift
      output reg [N+M-1:0]      mult1_acco,  // Current accumulation result
      output reg                rdy );

    always @(posedge clk or negedge rstn) begin
        if (!rstn) begin
            rdy            <= 'b0 ;