Use of for statement in Verilog

stay C In language , Frequently used for Loop statement , But in hardware description language for The use of statements is more C Language and other software description languages are quite different .
stay Verilog In addition to in Testbench( Imitation test incentives ) Use in for Out of loop statement , stay Testbench in for Statements are commonly used in generating excitation signals , But in RTL Level coding is rarely used for Loop statement . The main reason is for The loop will be expanded by the synthesizer into execution statements for all variable cases , Each variable occupies register resources independently , Each execution statement cannot effectively reuse hardware logic resources , It's a huge waste of resources . Simply put ;for The statement loops several times , Is to copy the same circuit several times , So the more cycles , The larger the occupied area , The slower the synthesis .
stay RTL Hardware description , Encounter a similar algorithm , The recommended method is to find out the timing requirements of the design first , Make one rea Type a counter . Accumulate along each clock , And judge the counter condition at each clock edge , Do the corresponding treatment , Reusable processing modules should be reused as much as possible , Even if all operations cannot be reused , Also used case Statement expansion processing .
For the following for Loop statement :
1 for(i=0;i<16;i++)
2 DoSomething();

The following code can be used to realize :
reg [3:0] counter;
always @(posedge clk)
if(syn_rst)
counter<=4'b0;
else
counter<=counter+1:
always @(posedge clk)
begin
case(counter)
4'b0000:
4'b0001:

......

default:
endcase
end

in addition , There are several grammatical details that need attention .for(i&#