Risc-v-qemu-virt in FreeRTOS_ Lock mechanism analysis of GCC

brief introduction

riscv  Provides  atomic  Instruction extension  (A)
freertos  Also provided   Locking mechanism , Let's see how the two rub together 

Related concepts

MUTEX( The mutex ) From the ”MUTual EXclusion
 Competitive state 
 Concurrency will produce race 
---
 We were  https://blog.csdn.net/u011011827/article/details/117690639  We have analyzed linux Competitive state of 
 Be careful  : 	 Soft interrupt  ,  Kernel preemption   yes  linux  A unique concept 
freertos  I won't support it SMP,  So it's single core , There are two reasons for the race of mononuclear 
	1.  interrupt 
	2.  Dispatch 
 and  freertos-riscv  There are two scheduling opportunities 
	1.  Active scheduling 
	2. systick(mtimer)  Interrupt function   Dispatch 

 therefore   about  freertos-riscv  Come on   , " Close the interrupt "  Namely   solve   Competitive   Method 
 But in fact , freertos  Of  " Locking mechanism "  Essentially   Namely  " Close the interrupt ", Not used riscv Atomic instructions for 

freertos lock API

https://blog.csdn.net/qq_26226375/article/details/123955528

./Source/portable/GCC/RISC-V/portmacro.h

 98 /*-----------------------------------------------------------*/                
 99                                                                                
100                                                                                
101 /* Critical section management. */                                             
102 #define portCRITICAL_NESTING_IN_TCB                 1                          
103 extern void vTaskEnterCritical( void );                                        
104 extern void vTaskExitCritical( void );                                         
105                                                                                
106 #define portSET_INTERRUPT_MASK_FROM_ISR() 0                                    
107 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
108 #define portDISABLE_INTERRUPTS()    __asm volatile( "csrc mstatus, 8" )        
109 #define portENABLE_INTERRUPTS()     __asm volatile( "csrs mstatus, 8" )        
110 #define portENTER_CRITICAL()    vTaskEnterCritical()                           
111 #define portEXIT_CRITICAL()     vTaskExitCritical()                            
112                                                                                
113 /*-----------------------------------------------------------*/


 Analyze the code implementation ,  I found it was just off   interrupt  ( Set up  mstatus  Medium  MIE  by  1)