Method of using inout signal in Verilog

Catalog

One 、inout How to use it in design documents

1.1、inout The first way to use

1.2、inout The second use of the implementation

1.3、inout Use summary

  Two 、inout How to use it in simulation test

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One 、inout How to use it in design documents

stay FPGA In the design process of , Sometimes we encounter two-way signals ( It can be used as output , Signals that can also be used as inputs are called bidirectional signals ). such as ,IIC In the bus SDA A signal is a two-way signal ,QSPI Flash During the four wire operation of the, the four signal lines are bidirectional signals . stay Verilog Keyword in inout Define bidirectional signals , Here is a summary of bidirectional signal processing methods .

1.1、inout The first way to use

　　 actually , The essence of bidirectional signal is composed of a three state gate , Three state gate can output high level , Low level and high resistance states , stay FPGA in , The structure of a three state gate is shown in the figure below ：

Describing this logic Verilog The code is as follows ：

module inout_top
(
input       I_data_in        ,
inout       IO_data          ,
output     O_data_out     ,
input       Control
);

assign IO_data = Control ? I_data_in : 1'bz ;
assign O_data_out = IO_data ;

endmodule

When Control by 1 when ,IO_data For export , Output I_data_in Value

When Control by 0 when ,IO_data For input , Assign the input signal to O_data_out

This code is in Vivado2015.4.2 Compilation environment RTL The picture is shown below

stay ISE14.7 Under the compilation environment of RTL The picture is shown below

 

 

It can be found in Vivado2015.4.2 Environmental Control The signal IBUF There's also a LUT, stay ISE14.7 In the environment Control A reverser is synthesized behind the signal , There's this LUT And the reason for the inverter is Control by 1 Only then IO_data Set to output , And in the Xilinx In a IOBUF Resource default T intention 0 when IO End is output ,T intention 1 when ,IO End as input , So the

assign IO_data = Control ? I_data_in : 1'bz ;//Control=1 when   As the output 

Change it to

assign IO_data = (Control == 1’b0) ? I_data_in : 1'bz ;//Control=0 when   As the output 

stay Vivado2015.4.2 Integrated under the environment RTL Figure below

stay ISE14.7 Under the environment of RTL The picture is shown below

 

 

obviously ,Vivado Environment LUT and ISE The inverter in the environment is missing , Saved 1 individual Cell resources .

1.2、inout The second use of the implementation

The above is the treatment inout The first way , The second treatment inout The way to signal is to call Xilinx Of IOBUF The original language ,IOBUF The primitive of can be found in Vivado2015.4.2 Of Language Templates Find .

Call the of this primitive Verilog The code is as follows ：

module inout_top
(
input   I_data_in,
inout   IO_data  ,
output  O_data_out  ,
input   Control
);

IOBUF #(
  .DRIVE(12), // Specify the output drive strength
  .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE"
  .IOSTANDARD("DEFAULT"), // Specify the I/O standard
  .SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
  .O(O_data_out),     // Buffer output
  .IO(IO_data),   // Buffer inout port (connect directly to top-level port)
  .I(I_data_in),     // Buffer input
  .T(Control)      // 3-state enable input, high=input, low=output
);

endmodule

  stay Vivado2015.4.2 Integrated under the environment RTL The picture is shown below

stay ISE14.7 Integrated under the environment RTL The picture is shown below

 

Obviously and   assign IO_data = (Control == 1’b0) ? I_data_in : 1'bz ; In this case, a comprehensive RTL Exactly the same as .

1.3、inout Use summary

utilize Verilog There are two ways to process bi-directional signals ：

　　1、 Write code

assign IO_data = (Control == 1’b0)? I_data_in : 1'bz ;
assign O_data_out = IO_data ;

　　2、 Exemplification IOBUF The original language

　　　　IOBUF #(
 　　　　 .DRIVE(12), // Specify the output drive strength
  　　　　.IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE"
  　　　　.IOSTANDARD("DEFAULT"), // Specify the I/O standard
  　　　　.SLEW("SLOW") // Specify the output slew rate
　　　　) IOBUF_inst (
  　　　　.O(O_data_out),     // Buffer output
  　　　　.IO(IO_data),   // Buffer inout port (connect directly to top-level port)
 　　　　 .I(I_data_in),     // Buffer input
  　　　　.T(Control)      // 3-state enable input, high=input, low=output
　　　　);

  Two 、inout How to use it in simulation test

Verilog Use in inout How to write and simulate - Baidu library