A collection of problems on improving working frequency and reducing power consumption in FPGA design

The essence of increasing the operating frequency is to reduce the delay from register to register , in short , Reduce various delays

• The circuit delay mainly includes three ：
  Register delay Tco（ The time delay is determined by the physical characteristics of the device ）、 Routing delay and combinational logic delay .

• Routing delay ：
  1、 Add clock constraints （ In general, add 5% The margin is appropriate ）
  2、 The wiring of relevant logic shall be as close as possible , So as to reduce the routing delay .

• Combinatorial logic delays ：
  1、 Cutting combinatorial logic , Reduce LUT cascade , When the output judgment condition is greater than four inputs , In general, more LUT The way to cascade , Then more delays will be introduced , Therefore, we should reduce the input conditions as much as possible , Thus cascading LUT And less . Cutting combinational logic often adopts pipeline technology , This is achieved by inserting registers between levels , Thus, the combinatorial logic between levels is reduced .
  2、 Remove the counter FSM. When we are designing a state machine , Sometimes the counter is used as a judgment condition , But the input is usually four input , The counter value is large , such as 111100, So you need LUT cascade , So we write the counter out of the state machine .
  3、 When there are dozens of states in the state machine , You can also cut , In a certain state, it can jump to a new small state machine .

summary ： The most effective way to increase the clock frequency is to avoid large combinational logic （ Try to meet the four input conditions , Reduce LUT Number of cascades ）.
Common technology ： By adding constraints 、 Assembly line technology 、 The method of cutting state improves the working frequency .

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Understand various power consumption

low power consumption , Simply speaking —— Reduce 0 and 1 Flip of .

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subject 1：

Which of the following measures will help to improve the frequency of design ( AD ).

A Combinatorial logic splitting B Reduce unnecessary register reset

C ram/fifo Output deposit D Reduce the number of signal fan outs

analysis ： Combinational logic splitting and reducing the number of signal fan outs can reduce the delay of combinational logic .
Fan out ：FPGA Inside , Fan out is an output connection / The number of secondary resources to be driven , Like driving 10 individual LUT Lookup table ;

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subject 2：
On sequential logic circuits Pipeline Design （ pipeline Design ） The correct statement is （ ACD ）？

A.Pipeline Can improve throughput

B.Pipeline It can reduce the cost of a single task latency

C.Pipeline It can increase the clock frequency

D.Pipeline It is necessary to cut the water line , The design shall balance the convection water line , To ensure that the timing is close

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subject 3：

The following methods to reduce power consumption , To reduce static power consumption ABE

A: Power consumption optimization of gate circuit

B: Multi threshold voltage

C: Gated clock circuit

D: Operand separation

E: Multiple supply voltages

CMOS Tube power consumption = Dynamic power consumption + Static power consumption Static power consumption ： Is the power consumption required when the clock is not working

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subject 4：
subject 1： Which of the following power consumption measures can reduce the peak power consumption ？ ——A

A Static module level Clock Gating
B Memory Shut Down
C Power Gating
D A big increase HVT The proportion

A： Because the peak loss usually occurs at the moment of clock reversal , and A The option is to add clock gating , Turn off the clock when we don't need it to turn .
B： Storage closed , When not accessed , Turn off the memory , It belongs to reducing static power consumption .
C： power gating , That is, when the module is not working , Turn off the power , Module sleep , Start the power supply when working , It also belongs to reducing static power consumption .
D： Transistors with high threshold voltage , The effect of increasing the threshold voltage is to reduce the sub threshold leakage current , It belongs to reducing static power consumption .
The question is controversial , The answer is different from two perspectives , In my submission A correct , Here we choose A.

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subject 5：
subject 2： Which of the following measures can reduce SRAM Dynamic power consumption of （ BC）.（ Dajiang FPGA Logic post B volume ）（ multi-select ）
A Do not visit SRAM when , Turn off the clock
B Do not visit SRAM when , Address lines do not flip
C Do not visit SRAM when , Write data lines do not flip
D Do not visit SRAM when , Put it Power down

D： First of all, for SRAM Come on , It belongs to static random access memory , Static means as long as power is applied , Data can be maintained , When the power is cut off , Data loss . therefore D Option cannot be used as a method to reduce loss .
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A： The main variable affecting dynamic power consumption is capacitor charging 、 Operating voltage and clock frequency . So in SRAM When not working , Close control SRAM The clock of ,SDRAM The data in is not lost , And it can reduce the dynamic loss .
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BC： Do not visit SRAM when , The address line and write data line are not flipped , It's equivalent to reducing CMOS Tube turnover , Therefore, the dynamic loss can be reduced .

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subject 6：
about 90nm Process chip , Legal voltage , Within the ambient temperature range , Which of the following situations has the fastest internal signal speed ：B

A: Low temperature , Low voltage

B: Low temperature , The voltage is high （CPU liquid nitrogen compression Can achieve overclocking ）

C: The temperature is high , Low voltage

D: The temperature is high , The voltage is high

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subject 7：

Explain what it means clock gating？ And explain why you should do it under normal circumstances clock gating？ Simply list the methods that are usually implemented ？

First, master the knowledge of reducing power consumption .

clock gating： Clock gating , It is a simple and effective method to reduce power consumption .
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The benefits of clock gating ： Clock gating generates a clock by combining logic gates , Thus, switching can be realized , Therefore, the temporarily unused clock can be turned off , Avoid the power consumption caused by useless clock reversal ., So as to reduce power consumption .
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Implementation method ： Set up a en The signal , Give Way clock and en Signals and operations .

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subject 8：
Understanding of assembly line design , The wrong is ：

A. Pipeline design will consume more combinatorial logic resources .

B. Pipeline design will increase the delay of the original channel .

C. The idea of assembly line design , Is to use the area in exchange for speed .

D. Insert pipeline in critical path , It can improve the system clock frequency .

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subject 9：
Which one has the greatest impact on the static power consumption of the chip D

A. Working mode . B. frequency . C. load . D. voltage .

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subject 10：
Without adding pipeline Under the circumstances , How to solve a problem critical path Of setup The problem of unsatisfied timing

A. Process library using more advanced processes .

B. Here it is path Insert register on .

C. Move some combinational logic circuits to the previous stage path On .

D. Reduce the clock frequency .

analysis ：B It's assembly line technology

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subject 11：

Which of the following optimization methods are speed optimization methods ： BC

A. Resource sharing . B. Critical path optimization . C. Assembly line . D. Serialization .

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subject 12：[NVIDIA]
Please reduce power consumption for the following circuits ：

Problem solving ：
First of all, power consumption is mainly caused by high and low level switching , This question examines the power consumption caused by clock signal reversal , We often use clock gating to solve the problem .
Clock gating ： Using combinatorial logic , To control the clock , Thus, it can be turned off when the clock is not used .
As shown in the figure below , Join in en Signal and operation , We can according to en Signal to control the clock signal .

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subject 13：
Which of the following items can help reduce test time（AB）

A. Increase Operation Voltage.

B. Increase scan shift clock frequency.

C. Utilize more scan IOs.

D. Insert gating logic.

analysis ： Increasing the voltage can shorten the time delay , Increase the clock frequency , It can reduce the working time . The more fans out, the greater the delay , The more combinational logic, the greater the delay .

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subject 14：

Electronic system design optimization , The main consideration is to improve resource utilization and reduce power consumption （ Area optimization ） And improve the running speed ( Speed optimization ) , The following methods ( A) It does not belong to area optimization .

A、 pipeline Design —— Sacrifice area for speed

B、 Resource sharing

C、 Logic optimization

D、 Serialization