FPGA learning notes: vivado 2019.1 project creation

Preface

• Recently bought a piece of 【 The punctual atoms 】 Vinci Pro FPGA Development board , Study FPGA Development related knowledge

• This FPGA Based on Development Xilinx Of xc7a35tfgg484-2, There are abundant resources

• Xilinx Now recommended development IDE yes Vivado, No longer recommended ISE, I use Vivado 2019.1, This software is huge , Take up about 50~70G The hard disk of

Create a project

• Create this part of the project , The process is relatively simple , Take a note here

• First of all, install Vivado 2019.1 , open Vivado 2019.1

• Click on 【Create Project】 Create a new Vivado engineering

• to Vivado Name the project , Be careful not to use Chinese directories 、 The name does not contain spaces 、 Special symbols
  

• Category of works , Default common ：【RTL Project】, So direct 【Next】 that will do
  

• You can not add the source file for the time being ,verilog HDL The source file , Such as hello.v, You can add after creating the project , You can also choose 【VHDL】 Language
  

• choice FPGA Model , This needs to choose the actual circuit board FPGA model , My development board is ：xc7a35tfgg484-2, stay 【Search】 In the search box , You can enter model , Filter out what you want FPGA Model
  

• Empty Vivado FPGA engineering , It's done
  

• Empty works are as follows , Later research and development FPGA The whole process of
  

Summary

• First create an empty project , Discovery is all the way 【Next】, Select pairs FPGA The model is OK , If you choose wrong , Can be changed later

• By understanding ,Vivado And support Command line , That is to say tcl Script development , This will be studied later

• Continue to study later Add source file 、 Simulation 、 comprehensive 、 Realization 、 Generate binaries , Download the process running on the board