What is the difference between'1 and'b1 when assigning values

stay sv When assigning a value in ,'1 and 'b1 What difference does assignment make ？

Give a simple assignment file , Look at the output

module tb;
    byte i;
    byte j;

    initial begin
        i = '1;
        j = 'b1;

        $display("**************");
        $display("i --> %b", i);
        $display("j --> %b", j);
        $display("*****End*******");
    end
endmodule

Variable i and j All declared as byte type （8 bit）, When used '1 When assigning values , All bits are 1; When used 'b1 When assigning values , Only the lowest is 1

What are the benefits

Let's make a change

module tb;
    parameter   SIZE = 8;
    bit [SIZE-1 : 0] i;
    bit [SIZE-1 : 0] j;

    initial begin
        i = '1;
        j = 'b1;

        $display("**************");
        $display("i --> %b", i);
        $display("j --> %b", j);
        $display("*****End*******");
    end
endmodule

Set a parameter , The output at this time should be consistent with that before the change

But if we subsequently change the value of the parameter , For example, we will SIZE The value of is changed to 16, Let's take a look at the results

module tb;
    parameter   SIZE = 16;
    bit [SIZE-1 : 0] i;
    bit [SIZE-1 : 0] j;

    initial begin
        i = '1;
        j = 'b1;

        $display("**************");
        $display("i --> %b", i);
        $display("j --> %b", j);
        $display("*****End*******");
    end
endmodule

You can see , use '1 The way of assignment , No matter how wide the seat is , All positions will be 1

And if we use the common Verilog Assignment method , When the bit width is 8 bit when

i = 8'hFF

When the bit width is changed to 16 bit when

i = 16'hFFFF

To achieve this effect , Many steps are simplified when changing

I looked back Verilog The book of , Found in fact Verilog There are also ways to achieve this effect , Is to use complement

i = ~0; //1 Complement operation of 
j = -1; //2 Complement operation of 

Take a look at the running results in this example

module tb;
    parameter   SIZE = 16;
    bit [SIZE-1 : 0] i;
    bit [SIZE-1 : 0] j;

    initial begin
        i = ~0;
        j = -1;

        $display("**************");
        $display("i --> %b", i);
        $display("j --> %b", j);
        $display("*****End*******");
    end
endmodule

It does , then SIZE The value of is changed to 32

All positions can still be 1

---