2022 spring move - core technology FPGA development post pen test question (original question and experience)

Preface ：

      2022 year 3 It was invested on the official website of Xindong technology in August FPGA post , I passed the resume screening on the same day , Got the chance of written examination . The topic of Xindong is regular , I prefer basic concept questions .10 Daodan topic selection ,5 Tao chooses many topics ,5 Simple answer .

Single topic selection （ Just remember 4 Avenue ）

1、 Synthesis is EDA Key steps in the design process , In the following description of synthesis ,（） It's wrong. . answer ：D
A、 Synthesis is the process of transforming one representation into another in the abstract design hierarchy .
B 、 Synthesis is to transform the high-level language of circuit into low-level language , But with FPGA/CPLD Net list file mapped to the basic structure of .
C、 In order to achieve the speed of the system 、 area 、 Performance requirements , Integration needs to be constrained , It is called comprehensive constraint .
D、 Synthesis can be understood as , The mapping process of software description and given hardware structure represented by circuit net list file , And this mapping relationship is unique （ That is, the comprehensive result is unique ).

2、 About the harm of asynchronous design , The following statement is wrong (). answer ：D
A、 The time delay of the signal varies with each layout , With PVT To change , Therefore, the reliability is very poor , And it's not easy to transplant .
B