The way of FPGA -- project scheme and FPGA design scheme of FPGA development process

Preface

FPGA The development of follows a certain process , We should learn to stand on the shoulders of giants FPGA Development , Listen to the experience of our predecessors , This post is excerpted from 《FPGA Road 》, Let's learn from the author FPGA Rich experience in development .

FPGA Development process

FPGA The development of the project should follow a certain development process .
For the general FPGA For projects , The brief development flow chart is as follows ：
Combined with the picture above, we can see , When you start developing a FPGA When the project is , First of all, we need to do some research and verification work in the early stage , Then make FPGA The design scheme , Only after that can we do FPGA Write code and start functional simulation at almost parallel time . Follow up function simulation , May be constantly to modify the previous writing FPGA Code , Until all the functional simulations pass , In order to enter the time series analysis . If there is a problem in timing analysis , You need to go back to FPGA Code writing link to modify , So back and forth until the timing analysis link passes , Then we can carry out board debugging work . If there is a problem in the debugging process and confirm that it needs to be modified FPGA Design code , Then go back to FPGA Code writing , So back and forth until the board debugging pass , To confirm the end of the project .
For unusual FPGA Project development , for example SOPC dependent FPGA Such design , It needs to be combined with its particularity , In a normal FPGA Make changes based on the project development process 、 add to 、 Delete or adjust , So as to be flexible in dealing with .
The next part , We will combine general FPGA Brief development flow chart of the project , Introduce the content of each process in detail 、 Methods and precautions , Let's talk about FPGA The development of the project first has an overall grasp .

Analysis and research of background knowledge

every last FPGA The birth of the project is to solve some practical problems , So every one FPGA Projects have their own background knowledge . This background may include mathematics 、 Physics 、 chemical 、 Biology, etc , It could also be more specific communications 、 control 、 Image and other secondary and even interdisciplinary fields . Because we are unlikely to be doing FPGA I have been involved in all these fields before the project , So if you want to make the FPGA Design , It is necessary to learn the relevant background knowledge 、 Master and analyze .
The time consumed in this link is based on FPGA The theoretical depth of the project is different , Generally speaking , Data caching 、 Simple control class FPGA Projects spend less time on this , And it's like modulation and demodulation 、 Video and audio compression and other projects with strong theoretical background , It will take a long time .
When learning background knowledge , Sure “ natural ”.

• First , Any subject field is very broad and profound .FPGA In the project that the designer contacts , Its theoretical background is bound to be varied , So in general ,FPGA Designers are amateurs in these disciplines . that , So-called “ The layman is watching , Experts look at the door ”, Because of the limited knowledge we have , Therefore, the study of background knowledge is often not deep enough . But Newton said ：“ If I see farther than others , That's because I stand on the shoulders of giants ”, you 're right , Because human beings have been accumulating knowledge since ancient times , The world will develop to today's highly civilized society , therefore , Don't doubt the formulas and theorems summarized in the book , Even though you may not understand their derivation , Unless you're Einstein （ Einstein's theory of relativity overthrows the universality of Newton's three laws , It shows that Newton's three laws are only an approximation when an object moves at a low speed ）.
• secondly , Any one of them FPGA Projects have a certain development cycle , And generally not too long , So it's impossible to give developers too much time to learn background knowledge . There are two main reasons ： One 、 Slow down a little , The market may be taken away by others . Two 、FPGA The integration of chips is getting higher and higher 、 Performance is getting better 、 Cheaper and cheaper , Many old system schemes may not be able to keep up with FPGA The pace of chip development .
  Of course ,“ natural ” There is also a kneading process . For in FPGA On the implementation of some very mature theoretical algorithm , that “ natural ” Yes. ; If you want to FPGA Simplify for the platform 、 Optimize or create some theoretical algorithms , Then we must have a deeper understanding of the relevant background knowledge .

Generally speaking ,FPGA Designers tend to focus more on FPGA Project specific chip implementation process , And ignore the full study of background knowledge , This is very, very wrong . Because the background knowledge is FPGA The soil of the project , It directly determines FPGA The growing environment of this small tree in the future . Pursue alone FPGA The specific chip implementation of the project does not require sufficient research on the background knowledge FPGA developer , It's like a hunter living in a primitive tribe , Even though you can use bows and arrows with great skill , It can't be compared to a sniper shotgun with a sight .

Design and development of project plan

The project plan is FPGA The first document output link in the basic development process , Good or bad project plan , It directly determines the whole FPGA Whether the follow-up process of project development is smooth or not . For some simpler projects , For example FPGA Realize an asynchronous serial port, etc , Maybe the role of the project plan is not obvious , It even makes people feel redundant and troublesome , That's a lot FPGA Developers do it on a regular basis FPGA One of the main reasons why I didn't write the project plan when I was developing the project , But once the project gets to scale , Or with a certain theoretical depth , Then the existence of the project plan is very necessary , Otherwise, rework in the future may cause a devastating blow to the confidence of developers or development teams .
The project plan is actually a kind of plan , Although the plan can't keep up with the changes , But without a plan, it's impossible . After the analysis and research of the background knowledge of the project taken over , Through the design and formulation of the project plan , Let developers have a global view of the project 、 The mastery of principle , And we can find some potential vulnerabilities in the project ahead of time , So as to avoid the rework caused by some unsolvable problems in subsequent development .
The design and formulation of the project plan is a relatively free link , There is no strict format for the final output document , But as a guiding document for the whole project , In the process of designing and making project plans, we should still grasp some basic principles .

Write clearly the background of the project

The first step of the project plan , It's about writing down why you want to do this project ？ What problem do you want to solve ？ What's the advantage of doing it ？ What are the application prospects of it ？ And so on and so forth . Because in general , Engineers serve companies or businesses , And profits are all companies 、 The ultimate goal of the enterprise , So if it's something that's not good for the company or the business , Then don't expect the boss to put in manpower 、 Material and financial resources . therefore , In order to make the project start smoothly , It is necessary to clarify the background of this project , Except that I am the boss of course .
Write clearly the background of the project , It is not enough to solve the above problems , Because these problems only focus on the project itself , Soldiers often say ,“ Enemy and know yourself , Only in this way can a hundred battles be won ”, So we also need to research the relevant companies and enterprises in the industry , Analyze the current form of the industry and the threat level of competitors , See what others are doing , To what extent , What are their advantages 、 What are the disadvantages , What advantages do you have 、 What are the disadvantages and so on . Otherwise, I will work hard to make a product , It is found that similar products of other companies in the market have been sold crazy for a long time , Then there will be only tears .

Write project requirements clearly

The project requirements mainly talk about what functions this project needs to complete , Relative to the background of the project , Project requirements need to be written in a little more detail .

• First , It is necessary to make clear the environmental status of the whole project operation . for example ： It should be a car system 、 Airborne systems 、 Shipboard system or handheld electronic equipment and so on .
• secondly , Be clear about what the input of the project is . for example , The input of sound processing related items should be sound , But the specific voice or instrument or anything else must be clear ; The input of image processing related items should be image , But whether it's face recognition or infrared imaging, we must make it clear .
• Third , Be clear about what the output of the project is . for example , The output of Coca Cola factory is Coca Cola , The output of KFC chain is hamburger 、 A chicken leg . that , The final output of our project is numbers 、 voice 、 Make sure to make clear the image or something .
• Fourth , Be clear about the specific needs of the project . for example , What are the requirements of the project for processing speed and performance , What are the requirements for space performance , What are the requirements in case of failure , What are the requirements for cost control .
• Last , List as many details as you can , This is also the most important part of the project requirements , The more complete the list of detailed requirements , The more comprehensive the plan can be considered in the subsequent development , So as to avoid some mismatches in the subsequent specific project development . for example , When the upper computer requests data, how long should we respond ？ What is the format of the reply packet ？ What is the meaning of each data ？ wait .

Write out the framework of the plan

The project needs to find sub links to solve the problem of what to do , The problem of how to do it will be solved by the scheme framework and algorithm details . Solve the problem of how to do , In fact, it is the process of seeking project solutions , This is the main purpose of the design and formulation of the whole project plan , It is also the guidance and basis of the whole project development process . If the background knowledge is FPGA The soil where this little tree grows , So the solution is like a gardener , For the growth of small trees to build a good stand , While protecting it, it can also grow in the right direction .
The scheme frame link is mainly responsible for the whole 、 Solve the problem of how to do it on the macro level . The advantage of it is that it can make people clear at a glance , So as to capture the design idea of the solution as soon as possible . In order to achieve this effect , The framework of the programme should preferably include the following ：

• One 、 Schematic diagram . Graphical description is easier to understand , And more image , It is very suitable to describe the solution of the project as a whole . Of course , In order to describe the scheme framework more clearly , It is better to attach some explanatory words to the block diagram of the other party's case , Briefly describe the function of each link in the block diagram and the relationship between the functional links .
• Two 、 soft 、 Hardware work division . Generally, the development of electronic related products is inseparable from the development of software and hardware , So in the scheme frame link , We should also explain the whole project software separately 、 Hardware part of the workload and work content .

Write the details of the algorithm

Algorithm details are another important part of the solution , It is an important complement to the programme framework . Contrary to the programme framework , Algorithm details are mainly from details and microcosmic , Solve the problem of how to do . This solution is not conceptual 、 The solution in principle , It's a very concrete solution . for example , If we come home from work and find that we don't have the key , So the tragedy happened , But I can't wait to die , At this point in the face of the current predicament , The framework of the scheme solves the problem of prying the door to enter 、 Turn over the window and enter 、 hit 110 Help or return to the company to get the key and other options . If you decide to turn over the window as the framework of the plan , So next , The details of the algorithm solve the problem of how to turn the window , For example, knock on the neighbor's door first , Then take the safety rope and tie it to your waist , The other end is held by the neighbor , Then step on the air conditioning bracket from the neighbor's balcony to enter the balcony and so on .

From the above analysis, we can see that , Algorithm details must be clear 、 detailed , It's better to be able to break it down into multiple steps , And make sure you follow these steps step by step , Can solve the problem .

Make sure the logic is complete

Is the project plan feasible , First of all, it depends on its logical completeness . If a plan is made , I can't justify myself , Make a contradiction 、 There are many omissions , Then the follow-up work is not necessary . That's why it's easy to rework a project if you just have a general idea in mind .
To ensure the logical completeness of the project plan , It's like doing a math problem , Make sure that every step of the plan is justified , The reasoning between steps should be sufficient or even necessary . such , The logic is complete , The plan has the significance of further implementation .

Make sure you achieve indifference

The project plan must have nothing to do with the implementation , The implementation here mainly refers to the use of some specific soft 、 Hardware or its development tools to design . for example , A similar description can appear in the project plan ——“ Use Pythagorean theorem to calculate the length of hypotenuse of right triangle ”, But it's better not to have a description like this ——“ stay FPGA Use two... Respectively DSP Hardware multiplication core resources to achieve multiplication operation , Then add up the results , And call the root IP The length of the hypotenuse of the right triangle can be obtained from the core ”. So why does the project plan have nothing to do with implementation ？

• First , The project plan is only the guidance of the project , Then we need to have a guiding look . Excellent managers have never been hands-on , Because first of all he doesn't have so much time , Secondly, it is also the performance of management incompetence .
• secondly , Truth needs to be tested by practice . Although the scheme has passed the sub links to ensure the logical completeness , however , This is only a preliminary guarantee that there are no obvious mistakes and loopholes in the scheme , To prove that the plan is completely right , It needs rigorous mathematical derivation , and , What is established in theory may not be realized in technology . therefore , Before the project plan is further proved to be correct , Any work that materializes is likely to become idle work .
• Last , All roads lead to Rome . Even if the plan is right , But implementation can be diverse . The same function , Can be in FPGA Implemented on , It can also be realized on single chip microcomputer , It can also be in PC Implemented on . After all, the project plan is still at the beginning of the project , At this time, the whole project may not be fully grasped , And it may be revised in the future , therefore , There's no need to be concrete at this time .

Make sure the writing is easy to understand

So called written intelligibility , In fact, it's to distinguish the intelligibility of the principle . As I said before , Finding out solutions is the main purpose of project design and formulation . And the solution is to solve the problem of how to do , It doesn't solve the problem of why . Why do you do this , It's actually a very difficult problem , It is contained in the analysis and research of background knowledge , Even if the project is successful, it is not clear . for example , You find that the coefficients of a set of filters have very good transition band attenuation characteristics , If it is true after simulation , Then you can use... In your project , As for why these coefficients are so good , In fact, there is not much need to spend time studying . This is also one of the fundamental differences between engineering and theory .
that , Why should the project plan be easy to understand in writing ？ This is from three aspects ：

• One 、 One project is often used for reference by other projects , So when there are similar projects in the future , You don't want to review your old projects as a headache ？
• Two 、 For some larger projects , It's often a team that works together , Then every member of the team should have an overall grasp of the project , This can only be achieved by reading the project plan . If your project plan is obscure , Or ambiguous , So it's strange that we can cooperate happily ！
• 3、 ... and 、 Similar to the second point , The person who makes the project plan may be the manager of the team , It may also be experts who are good at a certain field of science , Therefore, they often can not and can not personally carry out specific design and implementation . therefore , This is the time , The project plan becomes a bridge between the plan maker and the plan implementer . that , How well the bridge was built , It directly determines the realization of the final design 、 How bad .

Simulation and verification of algorithm feasibility

With FPGA The project is based on more and more theoretical knowledge 、 More and more in-depth , The importance of algorithm feasibility simulation and verification is more and more obvious . The following section , Will separate from “ Why? ”、“ When to do ” and “ How do you do it? ” Three aspects of this link are described in detail .

Why？

Although the full background knowledge research , And also gives a logical integrity of the project plan , But there is still a big gap between theory and practice , Especially when it comes to some specific algorithms , It is necessary to carry out serious simulation and verification , Otherwise, it will be “ Better believe than have no book ” The position of . So what should we pay attention to between theory and practice ？

• One 、 accuracy ！
  In reality, the signals are usually analog based , And ours FPGA perhaps PC They can only process digital signals , That's why people invented AD and DA chip . From analog to digital conversion , Generally speaking, it needs to be sampled and quantified , This involves time accuracy and amplitude accuracy and so on ; From digital to analog , Generally speaking, it needs to be transformed and interpolated , This also involves time accuracy and amplitude accuracy and so on .
  Let me give you an example . Suppose we're going to be in FPGA On the implementation of a simple function function , for example
  f(x) = x;
  If you need to find x = π Time output , Then there's the problem of accuracy . First ,π = 3.1415926……, It's a wireless acyclic decimal , So how can we π Input to FPGA In the chip ？ secondly , Through function expression , We know f(π) = π, Then the output is also a wireless acyclic decimal , So how can we calculate the result π Output to the outside world ？ thus it can be seen , The digital system can only perform an approximate calculation for the analog environment , As for the extent to which it needs to be approximated , It all depends on the accuracy of the system .

• Two 、 Accuracy ！
  In fact, the academic world is far from as lofty as you think 、 Holy , There are a lot of fish and eyes among them , When you come from the Internet or some literature 、 Some theoretical algorithms are found in the journal , Don't trust the performance index and application effect it promises . If I don't do some simulation and verification first , It's a very sad thing to find out in the end that being cheated .

• 3、 ... and 、 Level of detail ！
  “ It's on paper , We must know that we must do it ”！ Some things seem to be the same thing , It's another thing to do . We are engaged in FPGA Project development , In the end, all algorithms need to be in FPGA Implemented on the , Therefore, the understanding of these algorithms cannot be superficial , It must pass the simulation and verification in the early stage , In order to grasp some specific details of the algorithm . for example , Commentators often don't play football , That's why .

• Four 、 Undetermined degree ！
  Undetermined degree refers to some measures that need to be determined in combination with specific problems . for example ,“ increase FIR The order of the filter can make the filtering effect better ”, But how many steps can we reach the requirements of the project , This can only be judged according to the actual situation of our project , So it needs to be determined through the early simulation and verification . For some algorithms , Software simulation is not necessarily comprehensive , But we can give the basic conclusion quickly , And if it's directly in FPGA Try on , although FPGA Its parallelism makes it fast , But compile FPGA It's still up to PC Machine to finish , So for more complex projects , Even with minor changes , I'm afraid it takes hours to compile at a time , So time can really drag people down .

• 5、 ... and 、 Selectivity ！
  Selectivity is a trade-off consideration . for example , To sharpen an image , Some operators work well but have high computational complexity , Some operators are a little less effective but simple to calculate . that , At this point, we need to simulate the effect of the two operators respectively , According to the requirements of the system, select the appropriate operator to achieve .

• 6、 ... and 、 Degree of simulation ！
  The above points are mainly considered from the algorithm itself , in addition to , Algorithm feasibility simulation and verification link for future FPGA The function simulation of the design is also very helpful . for example , Need to use FPGA Implement a complex coding algorithm , So how do we know whether the output code stream is right or not during function simulation ？ It's simple , If we do enough simulation and verification in the early stage , that , For any original bitstream , Just use the simulation we wrote 、 As soon as the validation program runs , You can know what the correct output stream is ！

When？

that , When do I need to be right FPGA The feasibility of the algorithm is simulated and verified in the project ？ This is naturally after the confirmation of the project plan and FPGA Before the formal design begins . Because the project plan determines , The algorithm used can basically determine , Then I know what algorithm to simulate . After the feasibility of the algorithm is verified ,FPGA Design can start formally ; Otherwise, all the follow-up work is meaningless , At this time, we must return to the design and formulation of the project plan , Even the analysis and research of background knowledge , Get back to work .

Yes, of course , Not all FPGA In the project, the feasibility simulation and verification of the algorithm must be carried out , For some simple projects , For example, to realize an asynchronous serial port , In fact, there is no difficulty in algorithm . however , With FPGA Chips are used in more and more fields , The functions are becoming more and more complex , At present, most of them FPGA There is still no lack of such a link in the project . If your FPGA Project encounter 【Why？】 Any question mentioned in the section , So it's suggested that you have a basic simulation and verification of the algorithm .

How？

I know why to simulate and verify the algorithm , We also know the right time to simulate and verify the algorithm , Last , Let's see how to simulate and verify the algorithm .

• First , Software tools are recommended MATLAB、VC and LabVIEW, Of course , It's far more than that . among ,MATLAB and VC It's a pure text language programming environment , It's easier for people who have a foundation in software programming , It is suitable for complex pure algorithm simulation , A little bit of human-computer interaction ; and LabVIEW On the contrary , Graphic programming oriented , Easy to use , Even beginners can get started quickly , It has rich human-computer interaction means and is very simple to call , But programming is vulnerable to space constraints , Not conducive to the realization of too complex algorithm .

• secondly , The feasibility simulation and verification of the algorithm are suggested to follow the process from theoretical proof to algorithm simulation to environment simulation . Theoretical proof , The emphasis is on falsification , If you can , At the very beginning , Because it turns out that the algorithm in question , After the realization, 80% is not reliable ; Algorithm simulation , It is emphasized that the algorithm described by natural language and formula is realized by program , So we can see the approximate actual execution effect of the algorithm clearly , To make a judgment ; Environmental simulation , The emphasis is on fault tolerance , By simulating the noise and interference in the environment , To test the robustness of the algorithm .

• Last , Due to the feasibility of the algorithm simulation and verification links need more experience in software programming , So if it's team development , You can find someone with strong software design ability to take charge of . But for a good FPGA For developers , Programming is often not a big problem , After all, a lot FPGA Developers are all references 、 By contrast C Language learned HDL.

FPGA Development of design plan

Finally we can officially start FPGA On the design of , Are you in front of the book 、 Can't wait ？ But don't worry , When a writer creates a literary work, he must first outline it , So we're doing FPGA Before the code of the project is written, it is also necessary to FPGA The design of . Of course , For some simpler projects , The role of this link may not be very prominent , But as the FPGA The project is becoming more and more complex , The importance of this link is becoming more and more obvious .
FPGA The formulation of the design plan is FPGA The second part of the basic development process that takes the document as the output . This document , Most of the time, I write it to myself , because FPGA The process of making the plan , It's really just a FPGA The process of design conception , So if you can't write this document , Then you can't do the design well . If it's team development , So this document is something else FPGA Developer's guidance in specific code writing , It's more about the success or failure of the whole project .

To write FPGA The benefits of the design

Writing HDL Code first FPGA There are several advantages in the preparation of the design scheme ：

• One 、 We can FPGA There is a whole grasp of the difficulty of design .FPGA The plan is actually a project plan to HDL Code bridge , So the project plan is FPGA The difficulty degree of the implementation can be FPGA There is a general understanding of the design process .
• Two 、 We can FPGA The focus of the design has a whole grasp .FPGA The plan involves the whole project plan FPGA Realize the idea , therefore , We can compare which part of the project plan FPGA It's difficult to achieve , Which part of FPGA It's relatively easy to achieve , So that in the follow-up code development in a reasonable arrangement of time and energy . If it's team development , It is also more conducive to a reasonable task allocation .
• 3、 ... and 、 We can FPGA There is a rough grasp of the amount of resources used in the design .FPGA The plan is actually similar to FPGA Brief natural language description of design , Maybe we can't accurately estimate the usage of lookup table and register , But the general situation can be understood , Especially similar DSP nucleus 、BLOCK RAM Such rare resources , Well thought out words , It can almost be estimated accurately . Got hold of FPGA The amount of resources that may be used in the design , about FPGA Chip selection has a very important guiding significance ; If the chip model is fixed , Then it can also be done through FPGA Compare the number of resources inside the chip , To judge the right FPGA Whether the chip can carry the current design , If not , Then we need to readjust and allocate the resources used by each module .
• Four 、 Let's find some problems in the project plan ahead of time , Avoid more rework . I talked about it before. , The project plan is implementation independent , It doesn't matter what you are going to use as the carrier of the algorithm , And write FPGA Design code is closely related to implementation , It has to take into account FPGA Internal structural features , It involves the specific implementation carrier of the algorithm . since FPGA The design serves as a bridge , that , From project plan to HDL Whether this bridge can be built between code implementations , In fact, it is also an unknown number . Can the bridge be built or not , You need to try before you know , therefore , Before the bridge is completed , Build more tall buildings on the other side 、 Villas and commercial facilities may become a dead city . for example , I want to pass the project plan 1Gb/s The serial transmission rate to communicate , But the actual use of FPGA The chip only supports 200Mb/s, Then you have to go back to the project scheme making phase to modify .
• 5、 ... and 、 We can FPGA The design establishes a modular and hierarchical structure , To simplify the follow-up HDL The complexity of coding . Because in FPGA In the scheme design stage, a modular and hierarchical structure has been established , So when writing each piece of code specifically , Just make sure the interface is correct , You can focus on local design .

How to write FPGA design scheme

To write FPGA The following steps are recommended for the design proposal ：

• First step , Generalize the whole FPGA The design is divided into several parts according to the function . It is better to explain the functions of each part and the relationship between them with the overall system diagram , And define the main input and output of each part , namely FPGA The main interface relationship with the outside world and the various parts .
• The second step , For every big functional part , If it's necessary , You can repeat the first step , Until the function of each sub part is pure 、 A single （ notes ： It's not a simple function , Because if the function is simple , that FPGA There will be too many levels of design , Therefore, there will be too much adverse effects ）.
• The third step , For every pure sub part , Write a description of the algorithm . The explanation of ideas can be, but is not limited to, written description 、 Principle block diagram 、 List of formulas 、 Logical inference 、 Proof, etc .
• Step four , For each sub part of the algorithm ideas , Give a detailed FPGA Specific implementation description . The implementation specification can be, but is not limited to, a literal description 、 Structure diagram 、 Flow chart, etc .

Here we are. , Some people may be confused about the explanation of algorithm and FPGA The differences and connections between the specific implementation instructions . Actually , If a single sub part of the current project is another FPGA The whole content of the project , Then the algorithm of this sub part can be used as the project scheme of another project . Yes, of course , The project plan is completely implementation independent , But the ultimate goal of the algorithm explanation is more or less convenient FPGA Realized , Still need to think about FPGA The basic characteristics of , So think more about . and FPGA Specific implementation description , It's totally focused on algorithm FPGA Realization , Similar use FPGA What internal resources , What kind of digital circuit is used . for example , The function of the sub module is to carry out 63 Zoom in ; The algorithm idea is to multiply the input data directly ; The specific implementation may be the use of DSP Hardware multiplier and fix a coefficient to 63, Or multiply by 63 To multiply by 64 Then subtract yourself , And then use FPGA Easy to implement shift operation instead of 2 And so on .

FPGA Function code writing

Finally, it's time to write HDL The code link , The output of this link is the whole FPGA The core code of the design , I believe you must be very excited , But please be calm first , Because writing code is not a simple thing , It's very particular . Here is a brief introduction to some concepts and precautions .

• One 、 hierarchical 、 Sub module programming ideas .
  It's hard to write a module with 10000 lines of code , But writing a hundred modules with a hundred lines of code is relatively simple . That's why we have to go through it before we start writing functional code FPGA Design plan making link . When you make a plan, you will FPGA Hierarchical design 、 modularization , So it can be subdivided into pure functions 、 Single sub parts , So when you write code , You can focus on the experience to conquer each sub part one by one , And finally complete the development of the whole design .

• Two 、 What tools can I use to write code ？
  HDL The code is just a normal text file , The difference is that the suffix of the filename is usually “.vhd” perhaps “.v”, therefore , We can use any text editing software to HDL Code design . But to enhance HDL Code readability and comprehensibility , It is recommended that you use it to recognize HDL Language keyword text editing tools , For example, added HDL Grammar Library Ultraedit. however , Usually , If we have decided which company to use FPGA chip , So it's better to use the company's FPGA Integrated development environment to write code , for example Xilinx The company's ISE、Altera The company's Quartus etc. . in addition to , Some professional FPGA Simulation software can also support HDL The syntax of the code highlights , for example Modelsim、IUS etc. .

• 3、 ... and 、 Write code with consideration .
  HDL Code as FPGA The core carrier of design , Be sure to take... Seriously , It can't be done overnight . When it comes to coding , It's not enough to start from the function of design , You also need to consider the code for FPGA The allocation of resources on the chip and the impact on timing indicators . for example , If we already know that the speed of the system's master clock is relatively high , So when designing code, we should try to avoid writing complex composition logic with large delay , Otherwise, wait until thousands of timing problems are found in the timing analysis , It will make people have the impulse to rewrite the code . therefore , Write code with a global view , Pay attention to code , Because code is the foundation of design , If the code doesn't write well 、 Write thoughtlessly , Then the follow-up problems will be overwhelming .

• Four 、 Write code with determination .
  The third point is , Write code with consideration , But don't stop eating because of choking . Although code writing can not be sloppy , But don't be afraid , Don't dare to write . Have faith in your code , Of course, it needs a certain degree of training . please remember , Good code is not perfect code , It's efficient code , Because perfection just means code quality , But efficiency is reflected in two aspects —— Time and quality . In today's increasingly competitive environment , The code that can realize the required function of the project as soon as possible is the best code , And the perfect code , Having some experience FPGA Developers can write it out when they come , It just takes a certain amount of time . So we're doing HDL When the code is written , You don't have to be too strict with the details , Under the premise of ensuring that the quality of the code does not decline significantly , The pursuit of time efficiency is the key .

• 5、 ... and 、 Pay attention to backup and version control .
  When FPGA After a certain scale of design , Code writing often takes a long time , in addition to ,HDL The code will also make some necessary changes under the influence of the following links . that , At this time, it is very important for code backup and version control . For the moment , The recommended version control software is SVN, It's very powerful , The operation is also relatively simple . in addition to , It is also a more primitive backup method to pack compressed packets , But at this time we need to cooperate Beyond compare To determine the code changes between two versions , And it is best to cooperate with relevant documents to explain the code improvement of each version .

FPGA Functional simulation of the design

if FPGA The amount of code output in the process of writing functional code is not necessarily FPGA The most output code in the basic development process , You may not believe , So let's have a brief understanding of FPGA Function simulation of the design —— A link that also takes code as its effective output , For a more detailed introduction, please refer to 【 Function simulation 】.

One 、 Classification of simulation .

Since the title of this section is FPGA Functional simulation of the design , So there should be other simulation types decorated with different attributes .

you 're right , General statement ,FPGA The simulation in the design is divided into two categories , That is, pre simulation and post simulation . Pre simulation is also called functional simulation , The purpose is to analyze... Logically HDL The correctness of the circuit described by the code , Its simulation speed is much faster than post simulation , We can observe the circuit input as needed 、 Output port or HDL The waveform of any signal and register inside the code . Post simulation is also called sequential simulation , It is a simulation that takes into account the parameters of gate delay and the connection between various circuit units , So the simulation results are closer to the real application . However, a lot of timing information is considered in post simulation , The speed of later simulation is much slower than that of former simulation . And in order to consider timing information , Must be right HDL Code synthesis 、 Only after layout and wiring can we get the circuit situation , therefore HDL The correspondence between the internal signal in the code and the circuit is not so obvious , I can't even find a corresponding relationship , Therefore, it is difficult to observe the internal node waveform .

If you are more careful ,FPGA The simulation can be further divided into four categories , Code level simulation 、 Gate level simulation 、 Post mapping simulation and post routing simulation . among , Code level simulation , The simulation object is the original 、 Unprocessed HDL Code , This is what we usually call functional simulation ; Gate level simulation , The simulation object is HDL Gate level network table after code synthesis ; And after mapping simulation , The simulation object is that the gate level network table corresponds to FPGA Clustering of specific logical resources on , At this time, the gate delay information file in the circuit can be obtained for simulation ; Last , Simulation after layout and wiring , The simulation object has location information and connection information FPGA Clustering of logical resources , So we can consider gate delay and line delay information , This is what we usually call timing simulation .

Two 、 The function of functional simulation .

The function of function simulation , seeing the name of a thing one thinks of its function , Just make sure that HDL Correctness of code function . It is mainly reflected in two aspects ：

• First , At the beginning of function simulation , Will check HDL The correctness of code syntax , So we can point out some syntax errors in programming and some clerical errors in code writing .
• secondly , The function simulation link can simulate HDL The behavior of code functions , We can judge by the simulation results HDL Whether the function of code implementation is consistent with our expectation , So we can point out some right FPGA Solution understanding deviation and find out some programming errors .

Among the simulation types discussed above , The functional simulation is FPGA A necessary part of the basic development process , The others are optional . With incomplete statistics , The time consumed by the whole function simulation process is about the whole development cycle of the project 60% above , This shows the importance of .

3、 ... and 、 Right time for functional simulation .

Function simulation is not an independent link , It must be closely intertwined with the writing of functional code . First , The problems found in the functional simulation must be returned to the code writing link for modification , Therefore, if problems are found continuously, they need to be modified continuously, and then the modification can be confirmed through functional simulation . secondly , If you plan to write a complete FPGA All of the project HDL After the code, the function simulation will be carried out —— Quote a friend —— It's not you who will fix the problem , It's a matter of getting you . therefore , The recommended intervention time of functional simulation is to start the functional simulation of one module after finishing the writing of one module , After completing the compilation of several function related modules and individual function simulation , Start the function simulation of this function clustering , And so on , Until the top level simulation is completed .

Four 、 Functional simulation tools .

Generally speaking ,FPGA The integrated software development environment of the manufacturer includes tools for functional simulation , Generally speaking , For general needs , These simulation tools can deal with it freely .
But everything goes , It's hard to be good at everything , So compared with the products of professional simulation tools companies , These integrated development environment with simulation tools will inevitably appear to be dwarfed . Professional simulation tools also have three or six or nine grades , Generally speaking , More excellent simulation tools are mostly run in Linux In the environment , This is mainly due to Linux The efficiency of the system is high , So the simulation speed is faster , But it also requires users to have a certain Linux Basics , for example Cadence The company's IUS Simulation tools . Less powerful simulation tools are mostly run in Windows In the environment , because Windows Some of the inherent shortcomings of , The performance of simulation is limited , But due to the Windows Huge user base , This kind of simulation tool is easier to use , for example Mentor The company's Modelsim Simulation tools .
But simulation tools are still software after all , So its execution must be serial , and FPGA The circuits in are executed concurrently , To imitate in series , There must be a huge inflationary effect on time , So for a slightly more complex design , To simulate the HDL Code execution is equivalent to actual 1 Second simulation , May need to consume 1 More than days . therefore , With the restriction of software tools becoming more and more obvious , Companies have launched hardware prototype simulation accelerator products , This product can basically reduce the simulation time and the actual time to the same level , But the whole system configuration and use are very troublesome , And the price is often too expensive , for example Cadence The company's Cadence Incisive Palladium III Hardware simulation 、 Accelerator . For enterprises that are not specialized in large-scale project simulation 、 For institutions , There's no point in this kind of product .

5、 ... and 、 Pay attention to the backup of simulation code .

The function simulation code is compared with the function description code , More emphasis on backup , Not version control .
Why is version control not important , Because for the function description code , Minor changes to any sub module , Will affect the whole FPGA Design , To form a new version . And for functional simulation code , First , Any sub module changes , Does not affect the functional simulation code of other submodules , Even the simulation code for its own functions does not need to be modified . secondly , Functional simulation code is independent of each other , It's not like functional description code , By layering 、 Modular relationships eventually form a whole . for example , If one FPGA The function description code includes two modules ——A and B, So for modules A We need to write a set of functional simulation code , Let's call it simA, For modules B We need to write a set of functional simulation code , Let's call it simB. if FPGA The top module of the design is C, that C The implementation of must call A、B The corresponding instance of the two modules , But if we aim at C Module writing simC Function simulation code , that simC The function you want to achieve is not through a simple call simA、simB Two sets of function codes are OK , Must rewrite , therefore simA、simB、simC It's three separate sets of code . With FPGA The complexity of the project is increasing , There is always only one set of function description code , And there may be dozens of functional simulation codes 、 Hundreds of sets , But because of the pertinence of function simulation code , The frequency of modification will not be very high , So it doesn't need to spend too much energy on version control maintenance for function simulation code .
But the backup of function code is very important , Because once it's written FPGA Design function description code , Then in any FPGA In the process of basic development , As long as there are problems , Maybe we need to modify the core carrier . Any code that has been modified , Must be suspected of being bug Of , In order to verify the correctness of the modification , We need to re simulate its function , Therefore, it is convenient for us to confirm the correctness of design modification by keeping all functional simulation environment . in addition to , Function simulation code for the top module , It can be applied to other types of simulations with only a few modifications .

6、 ... and 、 The workload of functional simulation .

Go back to the question at the beginning of this chapter , Combined with the third 、 Introduction to Article 52 , We can know that for a common N Modules and sub modules FPGA Function code , You may need to write more than N Number of sets of functional simulation code to verify it , therefore , Generally speaking , Functional simulation is the whole FPGA The most important part of the basic development process is the output of code . Although these functional simulation code will not participate in the final FPGA On chip , But they play an indelible role in ensuring the success of the final project .

Last , From a FPGA From a developer's point of view , It is recommended that you use the convenient and powerful modelsim Tool for functional simulation .