Abbreviations of common English terms for IC R & D

Record some common IC The term

Software chapter ：

EDA Electronic Design Automation Electronic design automation ,IC A lot of... Needs to be used in the design process EDA Tools

VCS synopsys The company's digital front-end simulation tool

Verdi synopsys The company's digital front end debug Tools

FSDB Common waveform file format , use Verdi open

VCD value change dump A general waveform file format , Details , But the file is large

DC design compiler synopsys The company's digital synthesis tool

ICC IC Compiler synopsys A software used by the company for automatic layout and wiring , Many companies are using it

INNOVUS cadence The company's digital territory implementation tool 、

GDSII  Territory layout File format

PT prime time synopsys The company's static timing analysis tool

Vivado Vivado FPGA Manufacturer Xilinx company 2012 Integrated design environment released in

NCSIM cadence The company's digital front-end simulation tool

Modelsim mentor The company's digital front-end simulation tool , Also called QUESTASIM

Tessent mentor The company's DFT Tools , The market share is very high

Language ：

Shell  A common scripting language , and linux To combine closely

Python  Common scripting languages , Now there are many applications in artificial intelligence , Popular

Perl  A common scripting language , Very suitable for text processing

TCL  Tool command language , Script language for scheduling various software

Verilog  Hardware description language

SystemVerilog  Chip verification language

Agreement article ：

APB Advanced Peripheral Bus ARM company-launched AMBA One of the bus specifications , It is mainly used for the connection between peripherals with low bandwidth

AHB Advanced High-Performance Bus ARM company-launched AMBA One of the bus specifications , It is mainly used for the connection between high-performance modules

AXI Advanced eXtensible Interface ARM company-launched AMBA One of the bus specifications , One for high performance 、 High bandwidth 、 Low latency on chip bus

GPIO General Purpose Input Output Universal input / Output , Bus extender

HDMI High Definition Multimedia Interface High definition multimedia interface , It's a kind of digital video / Technical specification for audio interface

SPI Serial Peripheral Interface Serial peripheral interface , It's a high speed , full duplex , Synchronous communication bus

I2C Inter-Integrated Circuit I2C It is a common multidirectional control bus , There are only two wires

UART Universal Asynchronous  Receiver/Transmitter Universal asynchronous transmitter receiver transmitter , A common IP modular

CAN Controller Area Network ISO International standard serial communication protocol

MIPI Mobile Industry Processor Interface Mobile industry processor interface , Open standards and a specification for mobile application processors

OCP Open Core Protocol An efficient 、 Bus independent 、 Configurable and highly scalable interface protocol

PCIe Peripheral Component Interconnect Express Peripheral component interconnection standard , A common bus standard

USB Universal Serial Bus Universal serial bus , A high-speed bus protocol for connecting peripherals

Chip ：

IC Integrated Circuit The integrated circuit

LSI Large-scale integrated circuit large-scale integrated circuit

VLSI Very-large-scale integration vlsi

ASIC Application Special Integrated Circuit ASIC , The mainstream design process of chip design companies

FPGA Field Programmable Gate Array Field programmable gate array , And ASIC The process corresponds to

SoC System on Chip System on chip , Generally refers to a relatively large chip , Most contain CPU/MCU etc.

MCU Microcontroller unit Micro controller , Main control module

DSP Digital Signal Processing Digital signal processing module , IC The algorithm implementation of design companies often adopts

CPLD Complex Programmable Logic Device Complex programmable devices , and FPGA similar

IP Intellectual Property intellectual property right

FE Front End front end ,IC Front end design process in design

DV Design Verification  verification ,IC Verification process in design

BE Back End Back end , IC Back end design process in design

FULLCHIP fullchip level Commonly used in digital front-end design and verification , Refers to system level and chip level

GLS gate-level simulation Refers to gate level simulation in digital verification

LPS low power simulation Low power simulation , It is mostly used in low-power design verification

FM formal Formal verification , Net list and verilog Compare

STA Static Timing Analysis Static time series analysis , Numbers IC An important part of the design process

Netlist  Gate level grid , It's usually RTL Code Net list file generated by comprehensive tool

ECO Engineering Change Order At the end of the project , The chip design can only be modified at the gate level

DFT Design for Test A design method used to enhance chip testability , It's the number. IC Important steps in the process

ATPG Auto Test Pattern Generator Automatic test vector generation tool , DFT Common processes in

BIST Build in System Test Built in test system ,DFT Common processes in

JTAG Joint Test Action Group Joint test working group , It's an international standard test protocol , Mostly used for chip testing

CTS Clock tree synthesis Clock tree synthesis , It is an important process in the implementation of digital back-end

PD Physical design physical design , It generally refers to the layout design of digital back-end

PV Physical verification Physical verification , Verification required after the implementation of digital layout

APR Auto place and route Automatic placement and routing , It is the main process of digital back-end layout implementation

NDR Non-Default Route Non default connection rules , Important concepts in layout implementation

Layout  Territory , Refers to the final layout of the chip , Similar to design drawings in the construction industry

ERC Electronic Rule Check IC Design process Layout Check whether the layout complies with the electrical rules

LVS Layout versus Schematic Consistency check between layout and circuit diagram , After the layout is changed, check whether the layout is consistent with the gate circuit

DRC Design Rule Check After generating the layout, check whether it complies with the design rules provided by the process factory , Such as width 、 spacing 、 Area etc.

signoff  Acceptance mechanism , Acceptance criteria

Tapout  Tape-out , Send the final layout documents to the process plant for production

DAC Digital to Analog Convert Conversion circuit from digital signal to analog signal

ADC Analog to Digital Convert Conversion circuit from analog signal to digital signal

CAD Computer-Aided Design Computer aided design , Dedicated to helping provide software automation

CDC clock domain crossing Asynchronous clock timing check , Is an important step in Digital Design

DMA Direct Memory Access Direct memory access

RAM Random Access Memory Ram

ROM Read Only Memory read-only memory , It's nonvolatile

EEPROM Electrically Erasable Programmable Read-Only Memory Electrically erasable read only memory

DRAM Dynamic Random Access Memory Dynamic random access memory , The most common system memory

SRAM Static Random Access Memory Static random access memory

FLASH Flash EEPROM Memory Flash memory , At the same time RAM Features of fast reading data

LUT Look Up Table Lookup table , Used to store some data , It's essentially a RAM

IEEE Institute of Electrical and Electronics  Engineers Institute of electrical and electronics engineers

SPEC specification Instructions , Product specification , Each post engineer should write the corresponding spec

RTL Register Transformation Level Register transfer level , Use more of verilog To describe the hierarchy of

DUT design under test Design module to be tested

DUV design under verification and DUT The meaning is similar to

Testbench  Test platform , Digital verification builds a platform for testing

UVM Universal Verification Methodology Mainstream digital verification methodology , be based on systemverilog

REGRESSION  regression testing , In short, it means that all test cases run repeatedly , Until there are no errors and stabilize for a period of time

COVERAGE  coverage , Common terms for digital verification , It mainly includes code coverage and function coverage