Use of DDR3 (axi4) in Xilinx vivado (3) module packaging

1、 summary

        This article will be based on AXI4 Bus interface MIG IP The core is encapsulated with the designed read-write module , Designed as a similar FIFO Block RAM The black box of , In order to call in the project , simplify MIG IP The use of the core .

2、 Functional design

        encapsulation MIG IP The core is mainly used to comprehensively realize the following functions ：

（1） Start the operation according to the initialization success signal DDR3 chip .

（2） Easily configure the system clock and obtain DDR3 Read write clock .

（3） According to write busy （ Busy reading ） The signal reasonably designs the logic of external reading and writing data .

（4） Prepare according to writing （ Read preparation ） The signal reasonably designs the logic of external reading and writing data .

（5） Can dynamically configure DDR3  The data burst length of the chip .

（6） It is convenient to write or read data of multiple burst lengths at one time after one addressing .

3、 Encapsulation interface

        The following table lists the interface of the packaging module and the corresponding bit width 、 Direction information , It's sorted out 36 Ports , It can be roughly divided into three categories according to its main functions ：

（1） Connect to the development board  DDR chip （DDR2/DDR3 SDRAM） Physical port of the pin （Physical Interface）.

（2） Connect the clock of external logic 、 Reset 、 Initialize the equal signal port .

（3） Connect the data interaction port of external logic （User Interface）.

DDR3（AXI4） Package module interface design table

The name of the interface	A wide	Direction	describe
ddr3_dq	32	inout	Connect DDR Chip pins
ddr3_dqs_n	4	inout	Connect DDR Chip pins
ddr3_dqs_p	4	inout	Connect DDR Chip pins
ddr3_addr	15	output	Connect DDR Chip pins
ddr3_ba	3	output	Connect DDR Chip pins
ddr3_ras_n	1	output	Connect DDR Chip pins
ddr3_cas_n	1	output	Connect DDR Chip pins
ddr3_we_n	1	output	Connect DDR Chip pins
ddr3_reset_n	1	output	Connect DDR Chip pins
ddr3_ck_p	1	output	Connect DDR Chip pins
ddr3_ck_n	1	output	Connect DDR Chip pins
ddr3_cke	1	output	Connect DDR Chip pins
ddr3_cs_n	1	output	Connect DDR Chip pins
ddr3_dm	4	output	Connect DDR Chip pins
ddr3_odt	1	output	Connect DDR Chip pins
sys_clk_i	1	input	FPGA The system clock
clk_ref_i	1	input	Reference clock
init_calib_complete	1	output	DDR Initialization success signal , Highly effective
arst_n	1	input	FPGA System reset signal , Low efficiency
ddr_user_clk	1	output	The user reads and writes the clock
ddr_user_wr_en	1	input	Write enable
ddr_user_wr_addr	32	input	Write the address
ddr_user_wr_datalen	32	input	Total length of write data , The total length of multiple burst data
ddr_user_wr_busy	1	output	Write a busy signal
ddr_user_wr_data	256	input	Written data
ddr_user_wr_last	1	input	Write the end identifier of the data
ddr_user_wr_valid	1	input	A valid identifier for writing data
ddr_user_wr_ready	1	output	Write data preparation signal
ddr_user_rd_en	1	input	Reading enable
ddr_user_rd_addr	32	input	Read the address
ddr_user_rd_datalen	32	input	Total length of read data , The total length of multiple burst data
ddr_user_rd_busy	1	output	Read busy signal
ddr_user_rd_data	256	output	Read out data
ddr_user_rd_last	1	output	Read out the end identification of the data
ddr_user_rd_valid	1	output	Read out the valid identification of the data
ddr_user_rd_ready	1	input	Read data preparation signal

4、Verilog Code

        In code design , We will burst length （BURST_LEN） Set to 255（8'hff）, in other words , After the user gives a write address , Can be written continuously 256 It's a bit wide 256 Bits of data to  DDR3 In . that , After writing a group of burst data , The address increment should be 32 × 256 = 8192, namely 32'h00002000.

4.1 Package top layer

`timescale 1ps/1ps

module ddr_ram #
(
    parameter END_ADDRESS         = 32'hffffffff,
    parameter C_S_AXI_ID_WIDTH    = 4,
    parameter C_S_AXI_ADDR_WIDTH  = 32,
    parameter C_S_AXI_DATA_WIDTH  = 256
)(
    inout    [31:0]     ddr3_dq,
    inout    [3:0]      ddr3_dqs_n,
    inout    [3:0]      ddr3_dqs_p,
    output   [14:0]     ddr3_addr,
    output   [2:0]      ddr3_ba,
    output              ddr3_ras_n,
    output              ddr3_cas_n,
    output              ddr3_we_n,
    output              ddr3_reset_n,
    output   [0:0]      ddr3_ck_p,
    output   [0:0]      ddr3_ck_n,
    output   [0:0]      ddr3_cke,
    output   [0:0]      ddr3_cs_n,
    output   [3:0]      ddr3_dm,
    output   [0:0]      ddr3_odt,

    input               sys_clk_i,
    input               clk_ref_i,
    output              init_calib_complete,

    input               arst_n,
    output              ddr_user_clk,

    input               ddr_user_wr_en,
    input   [31:0]      ddr_user_wr_addr,
    input   [31:0]      ddr_user_wr_datalen,
    output              ddr_user_wr_busy,
 
    input   [255:0]     ddr_user_wr_data,
    input               ddr_user_wr_last,
    input               ddr_user_wr_valid,
    output              ddr_user_wr_ready,
    
    input               ddr_user_rd_en,
    input   [31:0]      ddr_user_rd_addr,
    input   [31:0]      ddr_user_rd_datalen,
    output              ddr_user_rd_busy,
 
    output  [255:0]     ddr_user_rd_data,
    output              ddr_user_rd_last,
    output              ddr_user_rd_valid,
    input               ddr_user_rd_ready
    );

    wire      clk;
    wire      rst;
    wire      mmcm_locked;
    reg       aresetn;
    
    // Slave Interface Write Address Ports
    wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_awid;
    wire [C_S_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr;
    wire [7:0]                        s_axi_awlen;
    wire [2:0]                        s_axi_awsize;
    wire [1:0]                        s_axi_awburst;
    wire [0:0]                        s_axi_awlock;
    wire [3:0]                        s_axi_awcache;
    wire [2:0]                        s_axi_awprot;
    wire                              s_axi_awvalid;
    wire                              s_axi_awready;

    // Slave Interface Write Data Ports
    wire [C_S_AXI_DATA_WIDTH-1:0]     s_axi_wdata;
    wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb;
    wire                              s_axi_wlast;
    wire                              s_axi_wvalid;
    wire                              s_axi_wready;

    // Slave Interface Write Response Ports
    wire                              s_axi_bready;
    wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_bid;
    wire [1:0]                        s_axi_bresp;
    wire                              s_axi_bvalid;

    // Slave Interface Read Address Ports
    wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_arid;
    wire [C_S_AXI_ADDR_WIDTH-1:0]     s_axi_araddr;
    wire [7:0]                        s_axi_arlen;
    wire [2:0]                        s_axi_arsize;
    wire [1:0]                        s_axi_arburst;
    wire [0:0]                        s_axi_arlock;
    wire [3:0]                        s_axi_arcache;
    wire [2:0]                        s_axi_arprot;
    wire                              s_axi_arvalid;
    wire                              s_axi_arready;

    // Slave Interface Read Data Ports
    wire                              s_axi_rready;
    wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_rid;
    wire [C_S_AXI_DATA_WIDTH-1:0]     s_axi_rdata;
    wire [1:0]                        s_axi_rresp;
    wire                              s_axi_rlast;
    wire                              s_axi_rvalid;

    assign  ddr_user_clk = clk;

    always @(posedge clk) begin
        aresetn <= ~rst;
    end

    mig_7series_0 u_mig_7series_0
    (
       // Memory interface ports
       .ddr3_addr                      (ddr3_addr),
       .ddr3_ba                        (ddr3_ba),
       .ddr3_cas_n                     (ddr3_cas_n),
       .ddr3_ck_n                      (ddr3_ck_n),
       .ddr3_ck_p                      (ddr3_ck_p),
       .ddr3_cke                       (ddr3_cke),
       .ddr3_ras_n                     (ddr3_ras_n),
       .ddr3_reset_n                   (ddr3_reset_n),
       .ddr3_we_n                      (ddr3_we_n),
       .ddr3_dq                        (ddr3_dq),
       .ddr3_dqs_n                     (ddr3_dqs_n),
       .ddr3_dqs_p                     (ddr3_dqs_p),
       .init_calib_complete            (init_calib_complete),
       .ddr3_cs_n                      (ddr3_cs_n),
       .ddr3_dm                        (ddr3_dm),
       .ddr3_odt                       (ddr3_odt),

       // Application interface ports
       .ui_clk                         (clk),
       .ui_clk_sync_rst                (rst),

       .mmcm_locked                    (mmcm_locked),
       .aresetn                        (aresetn),
       .app_sr_req                     (1'b0),
       .app_ref_req                    (1'b0),
       .app_zq_req                     (1'b0),
       .app_sr_active                  (),
       .app_ref_ack                    (),
       .app_zq_ack                     (),

       // Slave Interface Write Address Ports
       .s_axi_awid                     (s_axi_awid),
       .s_axi_awaddr                   (s_axi_awaddr),
       .s_axi_awlen                    (s_axi_awlen),
       .s_axi_awsize                   (s_axi_awsize),
       .s_axi_awburst                  (s_axi_awburst),
       .s_axi_awlock                   (s_axi_awlock),
       .s_axi_awcache                  (s_axi_awcache),
       .s_axi_awprot                   (s_axi_awprot),
       .s_axi_awqos                    (4'h0),
       .s_axi_awvalid                  (s_axi_awvalid),
       .s_axi_awready                  (s_axi_awready),

       // Slave Interface Write Data Ports
       .s_axi_wdata                    (s_axi_wdata),
       .s_axi_wstrb                    (s_axi_wstrb),
       .s_axi_wlast                    (s_axi_wlast),
       .s_axi_wvalid                   (s_axi_wvalid),
       .s_axi_wready                   (s_axi_wready),

       // Slave Interface Write Response Ports
       .s_axi_bid                      (s_axi_bid),
       .s_axi_bresp                    (s_axi_bresp),
       .s_axi_bvalid                   (s_axi_bvalid),
       .s_axi_bready                   (s_axi_bready),

       // Slave Interface Read Address Ports
       .s_axi_arid                     (s_axi_arid),
       .s_axi_araddr                   (s_axi_araddr),
       .s_axi_arlen                    (s_axi_arlen),
       .s_axi_arsize                   (s_axi_arsize),
       .s_axi_arburst                  (s_axi_arburst),
       .s_axi_arlock                   (s_axi_arlock),
       .s_axi_arcache                  (s_axi_arcache),
       .s_axi_arprot                   (s_axi_arprot),
       .s_axi_arqos                    (4'h0),
       .s_axi_arvalid                  (s_axi_arvalid),
       .s_axi_arready                  (s_axi_arready),

       // Slave Interface Read Data Ports
       .s_axi_rid                      (s_axi_rid),
       .s_axi_rdata                    (s_axi_rdata),
       .s_axi_rresp                    (s_axi_rresp),
       .s_axi_rlast                    (s_axi_rlast),
       .s_axi_rvalid                   (s_axi_rvalid),
       .s_axi_rready                   (s_axi_rready),

       .sys_clk_i                      (sys_clk_i),
       .clk_ref_i                      (clk_ref_i),
       .sys_rst                        (arst_n)
    );


    ddr_rw # (
        .BURST_LEN(8'hff),
        .ADD_ADDR(32'h00002000),
        .DATA_WIDTH(C_S_AXI_DATA_WIDTH),
        .ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
        .ID_WIDTH(C_S_AXI_ID_WIDTH)
    ) u_ddr_rw (
        .arst_n(arst_n && init_calib_complete),
        
        .ddr_user_wr_en(ddr_user_wr_en),
        .ddr_user_wr_addr(ddr_user_wr_addr),
        .ddr_user_wr_datalen(ddr_user_wr_datalen),
        .ddr_user_wr_busy(ddr_user_wr_busy),
        
        .ddr_user_wr_data(ddr_user_wr_data),
        .ddr_user_wr_last(ddr_user_wr_last),
        .ddr_user_wr_valid(ddr_user_wr_valid),
        .ddr_user_wr_ready(ddr_user_wr_ready),
        
        .ddr_user_rd_en(ddr_user_rd_en),
        .ddr_user_rd_addr(ddr_user_rd_addr),
        .ddr_user_rd_datalen(ddr_user_rd_datalen),
        .ddr_user_rd_busy(ddr_user_rd_busy),
        
        .ddr_user_rd_data(ddr_user_rd_data),
        .ddr_user_rd_last(ddr_user_rd_last),
        .ddr_user_rd_valid(ddr_user_rd_valid),
        .ddr_user_rd_ready(ddr_user_rd_ready),
        
        .end_addr(END_ADDRESS),
        
        .ddr_clk(clk),
        
        .m_axi_awid(s_axi_awid), 
        .m_axi_awaddr(s_axi_awaddr), 
        .m_axi_awlen(s_axi_awlen), 
        .m_axi_awsize(s_axi_awsize), 
        .m_axi_awburst(s_axi_awburst), 
        .m_axi_awlock(s_axi_awlock), 
        .m_axi_awcache(s_axi_awcache), 
        .m_axi_awprot(s_axi_awprot), 
        .m_axi_awqos(s_axi_awqos), 
        .m_axi_awvalid(s_axi_awvalid), 
        .m_axi_awready(s_axi_awready), 

        .m_axi_wlast(s_axi_wlast), 
        .m_axi_wdata(s_axi_wdata), 
        .m_axi_wvalid(s_axi_wvalid), 
        .m_axi_wready(s_axi_wready), 
        .m_axi_wstrb(s_axi_wstrb), 

        .m_axi_bresp(s_axi_bresp), 
        .m_axi_bvalid(s_axi_bvalid), 
        .m_axi_bready(s_axi_bready),
        
        .m_axi_arid(s_axi_arid), 
        .m_axi_araddr(s_axi_araddr), 
        .m_axi_arlen(s_axi_arlen), 
        .m_axi_arsize(s_axi_arsize), 
        .m_axi_arburst(s_axi_arburst), 
        .m_axi_arlock(s_axi_arlock), 
        .m_axi_arcache(s_axi_arcache), 
        .m_axi_arprot(s_axi_arprot), 
        .m_axi_arqos(s_axi_arqos), 
        .m_axi_arvalid(s_axi_arvalid), 
        .m_axi_arready(s_axi_arready), 

        .m_axi_rlast(s_axi_rlast), 
        .m_axi_rdata(s_axi_rdata), 
        .m_axi_rvalid(s_axi_rvalid), 
        .m_axi_rready(s_axi_rready), 
        .m_axi_rstrb(8'hff), 
        .m_axi_rresp(s_axi_rresp)
    );

endmodule

4.2 Read write module

`timescale 1ns / 1ps

module ddr_rw # (
        parameter   BURST_LEN   = 8'hff,
        parameter   ADD_ADDR    = 32'h00002000,
        parameter   DATA_WIDTH  = 256,
        parameter   ADDR_WIDTH  = 32,
        parameter   ID_WIDTH    = 4
    )(
        input   arst_n,
        
        input                       ddr_user_wr_en,
        input   [ADDR_WIDTH-1:0]    ddr_user_wr_addr,
        input   [ADDR_WIDTH-1:0]    ddr_user_wr_datalen,
        output                      ddr_user_wr_busy,
        
        input   [DATA_WIDTH-1:0]    ddr_user_wr_data,
        input                       ddr_user_wr_last,
        input                       ddr_user_wr_valid,
        output                      ddr_user_wr_ready,
        
        input                       ddr_user_rd_en,
        input   [ADDR_WIDTH-1:0]    ddr_user_rd_addr,
        input   [ADDR_WIDTH-1:0]    ddr_user_rd_datalen,
        output                      ddr_user_rd_busy,
        
        output  [DATA_WIDTH-1:0]    ddr_user_rd_data,
        output                      ddr_user_rd_last,
        output                      ddr_user_rd_valid,
        input                       ddr_user_rd_ready,

        input   [31:0]              end_addr,
        input                       ddr_clk,
        
        output  [ID_WIDTH-1:0]      m_axi_awid,
        output  [ADDR_WIDTH-1:0]    m_axi_awaddr,
        output  [7:0]               m_axi_awlen,
        output  [2:0]               m_axi_awsize,
        output  [1:0]               m_axi_awburst,
        output  [0:0]               m_axi_awlock,
        output  [3:0]               m_axi_awcache,
        output  [2:0]               m_axi_awprot,
        output  [3:0]               m_axi_awqos,
        output                      m_axi_awvalid,
        input                       m_axi_awready,
        
        output  [ID_WIDTH-1:0]      m_axi_wid,
        output                      m_axi_wlast,                            
        output  [DATA_WIDTH-1:0]    m_axi_wdata,
        output                      m_axi_wvalid,
        input                       m_axi_wready,
        output  [DATA_WIDTH/8-1:0]  m_axi_wstrb, 
        
        input   [ID_WIDTH-1:0]      m_axi_bid,
        input   [1:0]               m_axi_bresp,
        input                       m_axi_bvalid,
        output                      m_axi_bready,
        
        output  [ID_WIDTH-1:0]      m_axi_arid,
        output  [ADDR_WIDTH-1:0]    m_axi_araddr,
        output  [7:0]               m_axi_arlen,
        output  [2:0]               m_axi_arsize,
        output  [1:0]               m_axi_arburst,
        output  [0:0]               m_axi_arlock,
        output  [3:0]               m_axi_arcache,
        output  [2:0]               m_axi_arprot,
        output  [3:0]               m_axi_arqos,
        output                      m_axi_arvalid,
        input                       m_axi_arready,
        
        input   [ID_WIDTH-1:0]      m_axi_rid,
        input                       m_axi_rlast,                           
        input   [DATA_WIDTH-1:0]    m_axi_rdata,
        input                       m_axi_rvalid,
        output                      m_axi_rready,
        input   [DATA_WIDTH/8-1:0]  m_axi_rstrb,            
        input   [1:0]               m_axi_rresp
    );
    
    ddr_ram_wr # (
        .BURST_LEN(BURST_LEN),
        .ADD_ADDR(ADD_ADDR),
        .M_AXI_ID_WIDTH(ID_WIDTH),
        .M_AXI_ADDR_WIDTH(ADDR_WIDTH),
        .M_AXI_DATA_WIDTH(DATA_WIDTH)
    ) u_ddr_ram_wr (
        .arst_n(arst_n), 
        .end_addr(end_addr), 
        
        .ddr_user_wr_addr(ddr_user_wr_addr), 
        .ddr_user_wr_datalen(ddr_user_wr_datalen), 
        .ddr_user_wr_en(ddr_user_wr_en), 
        .ddr_user_wr_busy(ddr_user_wr_busy),
        
        .ddr_user_wr_data(ddr_user_wr_data), 
        .ddr_user_wr_last(ddr_user_wr_last), 
        .ddr_user_wr_valid(ddr_user_wr_valid), 
        .ddr_user_wr_ready(ddr_user_wr_ready), 

        .ddr_clk(ddr_clk), 

        .m_axi_awid(m_axi_awid), 
        .m_axi_awaddr(m_axi_awaddr), 
        .m_axi_awlen(m_axi_awlen), 
        .m_axi_awsize(m_axi_awsize), 
        .m_axi_awburst(m_axi_awburst), 
        .m_axi_awlock(m_axi_awlock), 
        .m_axi_awcache(m_axi_awcache), 
        .m_axi_awprot(m_axi_awprot), 
        .m_axi_awqos(m_axi_awqos), 
        .m_axi_awvalid(m_axi_awvalid), 
        .m_axi_awready(m_axi_awready), 

        .m_axi_wlast(m_axi_wlast), 
        .m_axi_wdata(m_axi_wdata), 
        .m_axi_wvalid(m_axi_wvalid), 
        .m_axi_wready(m_axi_wready), 
        .m_axi_wstrb(m_axi_wstrb), 

        .m_axi_bresp(m_axi_bresp), 
        .m_axi_bvalid(m_axi_bvalid), 
        .m_axi_bready(m_axi_bready)
    );
    
    ddr_ram_rd # (
        .BURST_LEN(BURST_LEN),
        .ADD_ADDR(ADD_ADDR),
        .M_AXI_ID_WIDTH(ID_WIDTH),
        .M_AXI_ADDR_WIDTH(ADDR_WIDTH),
        .M_AXI_DATA_WIDTH(DATA_WIDTH)
    ) u_ddr_ram_rd (
        .arst_n(arst_n),
        .end_addr(end_addr), 
        
        .ddr_user_rd_addr(ddr_user_rd_addr),
        .ddr_user_rd_datalen(ddr_user_rd_datalen),
        .ddr_user_rd_en(ddr_user_rd_en), 
        .ddr_user_rd_busy(ddr_user_rd_busy),
        
        .ddr_user_rd_data(ddr_user_rd_data), 
        .ddr_user_rd_last(ddr_user_rd_last), 
        .ddr_user_rd_valid(ddr_user_rd_valid), 
        .ddr_user_rd_ready(ddr_user_rd_ready), 

        .ddr_clk(ddr_clk), 

        .m_axi_arid(m_axi_arid), 
        .m_axi_araddr(m_axi_araddr), 
        .m_axi_arlen(m_axi_arlen), 
        .m_axi_arsize(m_axi_arsize), 
        .m_axi_arburst(m_axi_arburst), 
        .m_axi_arlock(m_axi_arlock), 
        .m_axi_arcache(m_axi_arcache), 
        .m_axi_arprot(m_axi_arprot), 
        .m_axi_arqos(m_axi_arqos), 
        .m_axi_arvalid(m_axi_arvalid), 
        .m_axi_arready(m_axi_arready), 

        .m_axi_rlast(m_axi_rlast), 
        .m_axi_rdata(m_axi_rdata), 
        .m_axi_rvalid(m_axi_rvalid), 
        .m_axi_rready(m_axi_rready), 
        .m_axi_rstrb(m_axi_rstrb), 
        .m_axi_rresp(m_axi_rresp)
    );

endmodule

Here we are ,MIG IP The nuclear package is completed , In need of use DDR3 Time can be directly connected with ddr_ram Modules interact .