Use of DDR3 (axi4) in Xilinx vivado (5) board test

1、 Test target

（1） verification DDR3 Whether the chip is initialized successfully ;

（2） verification DDR3 Whether the function of writing data is normal ;

（3） verification DDR3 Whether the data reading function is normal ;

（4） Verify whether the written and read data are consistent , Verify the correctness of reading and writing .

2、 Test ideas

（1） see DDR3 Whether the output initialization completion signal is pulled high after the board is powered on , And before the read-write operation  ready Whether the signal is normally pulled high ;

（2） Check whether the data can be written continuously ;

（3） Check whether the data can be read continuously ;

（4） Randomly select a written data , Find the corresponding read data , Is the comparison consistent .

3、 Expect signal waveform

（1）init_calib_complete： When the machine is powered on, it will be automatically raised for a period of time .

（2）ddr_user_wr_en： The state machine controls the reading and writing operation cycle to pull up .

（3）ddr_user_wr_datalen： Constant value 32'h0080000.

（4）ddr_user_wr_busy： After the state machine pulls up the write enable ,busy The signal is pulled high .

（5）ddr_user_wr_data：32'h1 To 32'hffffffff loop ,8 individual 32 Bit rounding 256 The bit .

（6）ddr_user_wr_last： A round of write operation ends ,last pull up .

（7）ddr_user_wr_valid： When writing valid data ,valid pull up .

（8）ddr_user_wr_ready： During the write operation ,ready pull up .

（9）ddr_user_rd_en： The state machine controls the reading and writing operation cycle to pull up .

（10）ddr_user_rd_datalen： Constant value 32'h0080000.

（11）ddr_user_rd_busy： After the state machine pulls up the read enable ,busy The signal is pulled high .

（12）ddr_user_rd_data： read out 32'h1 To 32'hffffffff loop ,8 individual 32 Bit rounding 256 The bit .

（13）ddr_user_rd_last： A round of read operation ends ,last pull up .

（14）ddr_user_rd_valid： When reading valid data is successful ,valid pull up .

（15）ddr_user_rd_ready： During the read operation ,ready pull up .

4、 Test condition setting

        Because the state machine setting is ： Write in succession WRITE_NUM Number , After a delay , Read all numbers consecutively , Repeat the next round of writing and reading . therefore , Need to be in VIVADO Set the trigger condition for raising the crawl read-write enable , And configure to display multiple windows （windows）, To find and check whether the numbers written and read are the same . The setting of the counting tool is shown in the following figure .

 

5、 Analysis of test results

        The following figure shows the captured 6 The overall waveform of signals read and written alternately by windows . From the signal in the figure （init_calib_complete） so ：DDR3 The initialization success signal output by the chip （init_calib_complete） It has been automatically raised after power on , And always .

        The following two figures show the waveform of the starting position of a round of writing and reading respectively . Before the write operation starts , It happens to be the end of the last reading operation , As shown in the figure ,ddr_user_rd_last Be pulled high , then ddr_user_rd_busy Pulled down , Indicates the end of the read operation .

        The position shown by the yellow line in the previous figure indicates write enable ddr_user_wr_en Be pulled high , Start a new round of write operation . In a new round of write operations , Data is written continuously （ddr_user_wr_data）, one by one clk Add 1.

        The position shown by the yellow line in the following figure indicates that reading is enabled ddr_user_rd_en Be pulled high , Start a new round of read operation . In a new round of read operations , Data is read out continuously （ddr_user_rd_data）, Read out data of waveform display one by one clk increase 1.

We randomly record a written data , Find and compare whether the read data is consistent . The figure below shows , Valid in writing （ddr_user_wr_valid） The first data written when pulling up is 256 Bit 37fc56fa … 37fc56fa.

  In the next reading operation , Find the read data , namely 256 Bit 37fc56fa … 37fc56fa, As shown in the figure below .

Record a written data randomly again , Find and compare whether the read data is consistent . The figure below shows , Valid in writing （ddr_user_wr_valid） The first data written when pulling up is 256 Bit 39fc5630 … 39fc5630.

  In the next reading operation , Find the read data , namely 256 Bit 39fc5630 … 39fc5630, As shown in the figure below .

Here we are , The verification results of the upper plate can preliminarily explain DDR3 Correctness of chip reading and writing .