Superscalar processor design yaoyongbin Chapter 5 instruction set excerpt

Instruction set system (Instruction Set Architecture, ISA) It is a general term for a series of contents that specify the external behavior of the processor , It includes basic data types data type, Instructions instruction, register register, Addressing mode addressing modes, Storage system memory architecture, interrupt interrupt, abnormal exception, And the outside IO The content such as .

Instruction set system is a bridge between software personnel and processor designers , Software personnel do not need to care about the hardware implementation details of the processor , Software can be developed only according to the collective system of instructions , Processor designers need to design a processor that conforms to the instruction set .

The hardware implementation of an instruction set system is called microstructure microarchitecture.

5.1  Complex instruction set reduced instruction set

Instruction sets can be essentially divided into complex instruction sets CISC And reduced instruction set RISC Two kinds of , The characteristic of complex instruction set is that it can accomplish many things in one instruction .

Early programs were written in assembly language or even machine language , For the convenience of programmers to write assemblers , Processor designers have designed increasingly complex instructions , These instructions can simplify the work of programmers . At that time, the memory capacity was very limited , Every byte in memory is precious , So the industry is more inclined to use high coding 、 Multiple operands and instructions of unequal length , It can make one instruction do as many things as possible , And reduce the occupation of memory . meanwhile , Registers are a more expensive thing , At that time, the processor could not put a large number of general-purpose registers , and , With the increase of the number of general registers , It takes up more memory , These reasons lead processor designers to complete as many tasks as possible in one instruction . The design of complex instruction sets seemed logical at that time , Only in RISC After the concept of , This complex set of instructions is called CISC.

Although many features of complex instruction set make code writing more convenient , At that time, these complex instructions needed several cycles to be executed , And most of the complex instructions are not used by the program , At the same time, the number of general registers in the complex instruction set is too small , This causes the processor to frequently access memory , As the speed gap between processor and memory increases , Frequent access to memory will reduce the execution efficiency of the processor . To overcome these shortcomings , We need to reduce the complexity of processor design , To allow more silicon area to place registers , This produces a reduced instruction set . It only includes the instructions often used in the program , This greatly reduces the silicon area of the processor , And it is convenient for pipeline to realize , The execution speed and power consumption of the processor are reduced , And those complex operations are realized through subroutines .

The reduced instruction set uses a rich number of general-purpose registers , All operations are done between general registers , To interact with storage , You need to use a dedicated access memory load/store Instructions , They are responsible for exchanging data between registers and processors .

RISC The length of instructions is generally equal , It greatly simplifies the design of decoding circuit in processing , It is also convenient for the realization of assembly line , But compared with complex instruction set , The reduced instruction set requires more instructions to complete the same function , Cause it to occupy more program memory , Although storage is very cheap now , But it can lead to Cache Listing of missing rate , To a certain extent RISC The execution efficiency of the processor is reduced . It's more popular now RISC Yes ARM,MIPS and PowerPC wait .

Now? RISC It can also reach hundreds , And the execution cycle is not fixed ; and CISC, for example x86 Instruction set , It also converts most of the instructions into RISC Instruction to execute .

5.2  Concise instruction set overview

5.2.1 MIPS Instruction set

differ ARM,MIPS Is a firm RISC The fundamentalist ,MIPS Instruction set is the simplest and purest reduced instruction set . stay MIPS There are three basic instructions in the instruction set .

 MIPS The length of the instruction is 32 position , It will be divided into different areas , among op It's called the opcode , Used to give the type of instruction , stay MIPS in , All instructions can be divided into three basic types I-Type,J-Type,R-Type.

JRI-Type Types can be used directly 16 Immediately ;

J-Type Format instructions use 26 The immediate number of bits , namely target, Generally used for jump type instructions ;

R-Type Type instructions operate on registers ,rs and rt Used as source register and destination register respectively ;R-Type It includes a large number of instructions , So we need to use func Make a further distinction between instructions , and sa Is specially used for shift instructions .

MIPS Instruction use of instruction set op Distinguish ,op be located Bit[31:26];op There are branches and jumps ,load、store、special type ;

CLZ Instruction is used to find the data in a specified register , Starting from the high position 0 The number of , and CLO The instruction is used to find the sequence starting from the high order 1 The number of ;

stay MIPS Delay slots that support branch instructions in the instruction set branch delay slot, After the branch instruction , Generally speaking, the compiler is responsible for a relatively independent , Instructions that do not rely on branch instructions are placed in the delay slot , This instruction usually comes from the front of the branch instruction , Whether or not the branch instruction is adjusted , It will all execute . In this way, even if the branch instruction jumps , There is no need to erase the instructions in the delay slot from the pipeline . This method makes it more efficient for ordinary processors with short pipeline in the early stage , But in deep pipelined superscalar processors , The number of instructions contained in the delay slot also increases , There is no way to find so many irrelevant instructions in the delay slot , Therefore, only the control collar can be filled into the delay slot NOP, This does not increase the execution efficiency of the processor .

Modern superscalar processors rely on accurate branch prediction techniques to process branch instructions , Delay slots have lost their significance in this kind of processor .

In determining the type of instruction op Area , One more COP0, It uses to define some special instructions to access the coprocessor , It cannot be used without expiration rs register . This part defines   Two instructions ,MTCO and MFCO, Used to transfer data between coprocessor registers and processor registers . The processor cannot directly operate the registers in the coprocessor , Because in the encoding of instructions, there is no way to directly encode the registers in the coprocessor .

5.2.2 ARM Instruction set

ARM The length of the instruction is 32 position .arm Instruction set more or less draws on some characteristics of complex instruction set , Try to do a lot of tasks in one instruction , This is different from MIPS Instructions .ARM Instruction sets are summarized into three types Data Processing,Data Transfer and Branch.

 （1）Cond：condition, because ARM Command set , Each instruction can be conditionally executed , This part is used to judge whether the condition of instruction execution is true ;

（2）F：instruction format, Used to distinguish the types of instructions , Such as DP,DT,BR type ;

（3）I：immediate, If this one is 0, Then the second operand in the instruction operand2 It's a register , Otherwise, the second operand is an immediate ;

（4）Opcode： Basic operation types of instructions ;

（5）S：set condition code, When this bit of an instruction is set to 1, Indicates that the operation of this instruction will affect the status register CPSR Value , Usually, an instruction is appended S To represent this function ;

（6）Rn： The first operand in the instruction , From register ;

（7）Operand2： The second operand in the instruction , It may come from registers , It can also be immediate ;

（8）Rd： Destination register , Store the result of instruction operation

When the second operand is an immediate , It's not a simple way to put instructions 12 Bit Operand2 Are used to express 12 Immediately ,ARM Think 12 The immediate number of bits indicates that the range is too small , In order to expand the representation range of immediate numbers , In the command 12 Bit Operand2 It's divided into two parts ,

In the figure rotate_imme and imme_8 Two parts , By way of 8 A data immed_8 Rotate right even digit , You can get one 32 The immediate number of bits . But even so ,ARM A lot of 32 The immediate number of bits is illegal , Cannot be directly encoded in instructions , Only a few 32 Bit immediate is legal .

If the compiler finds LDR In pseudo instruction 32 Bit immediate is illegal , You need to put this 32 The immediate number of bits is put into the text pool literal pool, Then use a PC dependent load Instruction to get this immediate . stay ARM In the program , Text pool means that the program memory is located behind the program area , A space for storing constants .MIPS The processing method of is more concise and efficient , Directly use two ordinary instructions to get 32 Immediately , Therefore, efficient execution can be achieved in superscalar processors .

stay ARM in , because PC Register is a general register defined by instruction set , So it can be used directly in instructions .

In superscalar processors , Access to memory requires TLB and Cache And a series of components , Any miss Will cause the reduction of execution efficiency .

In addressing mode , because MIPS and ARM All are RICS processor , There is no essential difference , An operand can exist in an instruction as an immediate number , It can also exist in general registers in the processor , It can also exist in memory , The immediate number existing in the instruction can be directly used by the processor , Therefore, this addressing method is the most efficient .

But inside the processor , Due to the instruction encoding length 、 Limitations such as silicon area and speed , The number of registers is generally limited , Therefore, only a small part of the used data can be stored in the register . Any data can be stored in the memory , It has a large capacity , But the access speed is generally slow , Although this addressing method is not very efficient , But the most widely used . In order to speed up this addressing , It is generally used in processors Cache.

Addressing mode ：

 5.3 load and store Instructions

5.3.1 load Instructions

stay MIPS Command set , Basic load Include LB,LBU,LH,LHU and LW Five instructions ：

（1）LB Instruction is used to read a byte of data from memory , Expand its symbol to 32 position , Then put it into the general register inside the processor , Handle signed numbers ;

（2）LBU Instruction is used to read a byte of data from memory , Expand its unsigned to 32 position , Then put it into the general register inside the processor , Handle unsigned numbers ;

（3）LH Instruction is used to read half a word of data from memory , Expand its symbol to 32 position , Then put it into the general register inside the processor , Handle signed numbers ;

（4）LHU Instruction is used to read half a word of data from memory , Expand its unsigned to 32 position , Then put it into the general register inside the processor , Handle unsigned numbers ;

（5）LH Instructions are used to read a word of data from memory , Then put it into the general register inside the processor ;

stay MIPS in , be-all load The memory address used by the instruction comes from the sum of base address and offset ,Rs+offset, among Rs Is the value of a general-purpose register ,offset From the instruction 16 Immediately .

5.3.2 store Instructions

stay MIPS Command set , Basic store The instructions include SB、SH and SW Three ：

（1）SB Instructions are used to put 32 Low bit of general purpose register 8 Put bits into memory ;

（2）SH Instructions are used to put 32 Low bit of general purpose register 16 Put bits into memory ;

（3）SW Instructions are used to put 32 Bit general register into memory ;

Because for writing data in memory , Just put the contents specified in the register in the specified position , It doesn't matter whether it is a signed number .

stay RISC In the processor ,Load/store When using instructions, you should pay attention to the problem of the size end .

Small end format little endian Put the low byte of a data in the low address of the memory , And the big end format big endian Then put the low byte of a data into the high address of the memory .

stay load/store On the order ,ARM and MIPS There are two main differences ：

（1） Before support / Post indexing (pre-index/post-index) The addressing mode of , This addressing method can be summarized into two tasks .

Task a ： Carry out the ordinary load/store operation ;

Task 2 ： change load/store The value of the address register in the instruction .

in other words , Use the addressing mode of fore-and-aft indexing , One load/store After the instruction is executed , The register storing the address can be automatically added and subtracted , In this way, you can operate on a continuous address space .

MISP Do not use this addressing method ？ There are two reasons ： First, this addressing method of fore-and-aft indexing is no longer in line with RISC The original idea , stay RISC The idea of , More things are left to software , This can reduce the complexity of hardware design , So as to obtain higher hardware performance ; Second, in 32 Bit MIPS In the encoding of instruction set , about load/store Type of instruction , There is no space to encode the pre and post indexing function .

（2） Degree register transfer instruction LDM/STM, Can be in one instruction , Put a piece of data with consecutive addresses in memory into multiple registers , Or put the contents of multiple registers into a continuous address space in memory , At the same time, it can also change the contents of the address register in the instruction . But it's actually ARM Before and after treatment ,LDM/STM Such instructions also need to consume multiple cycles to complete , The number of cycles required depends on the number of registers to be transferred . At this time, it creates an illusion for programmers ： So many tasks have been completed in one instruction , And it can also save instruction storage space . Saving program storage space means lower I-Cache Of miss rate. But in superscalar processors ,LDM/STM Because it contains multiple destination registers and source registers , It's hard to deal with it directly , Need to take some   Special measures .

5.4  Calculation instruction

MIPS The types of calculation instructions in the instruction set include arithmetic 、 Logic 、 displacement .

5.4.1  Addition and subtraction

stay MIPS in , Addition instructions are divided into signed and unsigned addition . When addition overflows overflow when ,ADD The instruction will generate an exception exception, At this time, the calculation result will not be written to the destination register ; and ADDU Will not pay attention to overflow , No exception will be generated, and the result will still be written to the destination register .

If an exception occurs in the pipeline processor , Instructions that enter the pipeline after this abnormal instruction should be erased from the pipeline , These instructions should not change the state of the processor , The pipeline will take new instructions from the entry address corresponding to the exception handler to execute . In ordinary processors with short pipelines , This operation will not cause too much performance loss , But for superscalar processors with deep pipelines , The exception processing needs to wait until the instruction that generates the exception becomes the oldest instruction in the pipeline ( That is, when you retire ), Then you need to erase the instructions in the whole pipeline , And restore the state of the processor .

Reduce operation SUB and SUBU similar , There is no subtracter inside the processor , It is realized by adder , Because in the operation of binary complement ,A-B=A+(~B)+1.

By comparison ,ARM The processing efficiency is higher when the addition and subtraction instructions overflow , For example, its implementation ADD When the command , You can choose to save the state of the result in the status register , stay ARM This status register in is called CPSR, The following instruction value determines whether it executes .

Of course ,ARM Instructions to do so also have a price , Because every instruction can be conditionally executed , Then each instruction needs to contain 4 Bit condition code , This makes the encoding space in the instruction that can be used to address registers smaller , therefore ARM There are only 16 individual , and MIPS There is 32 individual . When the number of general registers is large , The processor can reduce the number of memory accesses , This increases the efficiency of program execution .

5.4.2  Shift instructions

MIPS In the shift instruction of , No V Shift instructions for , An operand is an immediate number , The belt V Shift instructions for , Both operands are general purpose registers .

The instruction to shift left will be supplemented in the lower part 0, For the operation of moving right , It is divided into logical right shift and arithmetic right shift . For logical shift right , The part vacated in the high position is used 0 Add ; And arithmetic moves right , The vacated part of the high bit is filled with the sign bit of the original data . Therefore, shift the signed number to the right , You need to use arithmetic shift right , For unsigned right shift, we need logical right shift .

stay ARM There is no special shift instruction in , This is because ARM Most of the operation instructions in can shift operands before operation . Integrate shift operation and operation into one instruction .

5.4.3  Logical instruction

MIPS The logic instructions in mainly complete and 、 or 、 Not 、 XOR operations . stay ARM There are instructions with similar functions in , Logical operation instructions cooperate with immediate numbers , It can do a lot of things , for example ：

（1） Bit shielding function , Selectively mask some bits in a register ;

（2） The function of calculating remainder , The restriction requires that the divisor must be 2 Omega to an integer power ;

5.4.4  Multiplication instructions

MIPS in MUL The instruction will be two 32 Multiply bit source registers , And lower the multiplication result 32 Bit into destination register , When the multiplication result is greater than 32 When a , It will definitely lead to the situation that the result of multiplication cannot be completely put into the register , Pay attention to when programming ;

stay ARM Instruction set China , You can directly specify two general registers in the instruction to store the result of multiplication , In this way, you can directly perform other operations on the result of multiplication .

5.4.5  Multiply and accumulate instructions

Multiply and accumulate instructions MADD Sign multiply two operands , And automatically match the result of multiplication with Hi/Lo The data in the register is added , Then write the result of the addition to Hi/Lo In the register .

Multiply and subtract MSUB It is also a signed multiplication of two source operands and a little grandma , And then from {Hi,Lo} The result of subtracting the multiplication from the register , In essence , It is also a multiplication and accumulation operation .

5.4.6  Special calculation instructions

MIPS There are two special calculation instructions , namely CLZ and CLO,CLZ The instruction is used to calculate , Starting from the highest position 0 The number of .CLO Essence and CLZ equally , Just reverse the contents of the register , You can use CLZ Instruction hardware CLO Function of instruction .

5.5  Branch instruction

All instructions that can change the order of execution in a program are called branch instructions ,MIPS There are two kinds of branch instructions in ：（1） Unconditional execution , stay MIPS called Jump Instructions （2） Conditional execution , stay MIPS Is called branch instruction , These instructions are executed only when certain conditions are met , Equate to ARM Conditional branch instruction .

Branch instruction PC Value and immediate value are added to calculate the new destination address .

All with B The first branch instruction requires conditional judgment , Only when the condition is true can the branch instruction be executed , If the conditions don't hold , You can ignore this branch instruction , It's like this branch instruction doesn't exist .

ARM Judge when branching instructions CPSR Whether the state in the register meets the requirements .

for example MIPS Of BEQ How to use it ：

BEQ r1, r2, offset;

and ARM It is ：

BEQ LABLE1

When this instruction is executed , Direct reading CPSR The contents of the register , Judge Zero Sign a Z Whether it works , If effective , Indicates that the previous instruction satisfies the same condition （ For example, the last instruction is a comparison instruction ）, The jump to LABLE1 The local execution of , Otherwise, continue to execute in sequence .

stay MPIPS in , The jump range of branch type instructions is only +-/128KB, If you want to get a larger jump range , have access to J or JAL Instructions , These two instructions contain 26 Immediately .

Compared with PC-relative Branching mode , such PC-region The advantage of this method is ？ If a program is located in 256MB Within the range of alignment , Use this PC-region Branch instructions for , You can jump directly to any place of the program ;

If 256MB The jump range of is still not enough , You need to use JALR Instructions , This instruction directly uses a 32 The value of bit general-purpose register is used as the destination address of jump , So you can jump to 4GB Anywhere in the world .

stay ARM Command set , Execute one instruction at a time , You can choose whether to write the status of the instruction result to the status register CPSR in , stay CPSR Whether the result of the instruction recorded in is 0、 Comes at a time 、 negative , Whether there is overflow and other information , The following instructions can be based on CPSR Register to determine whether to execute . And because there is no branch instruction , There is no performance degradation caused by branch prediction failure .

But this advantage is not absolute , When a branch block branch block When it gets big , The number of instructions that require conditional execution will become a lot , At this point, the advantages of this method will become disadvantages , And it will bring extra trouble to register renaming .

More Than This , There are other costs for each instruction to execute , In every instruction , All need to include the condition code that encodes the condition condition code, It is used to encode the conditions used by this instruction , stay ARM This condition code in the instruction set occupies Bit[31::28].

however , Whether or not this instruction needs to be executed , Every instruction will have 4 Bit condition code , Therefore, there are fewer resources in the instruction that can be used to encode general-purpose registers .

5.6  Miscellaneous instructions

For example, instructions to access the coprocessor , Instructions that generate software interrupts , And debugging related instructions .

stay MIPS In the processor , All control registers used to control the execution of the processor are placed in the first coprocessor , The number of this coprocessor is 0,. But the processor cannot directly manipulate the coprocessor through instructions 0 Register in , Because there is no space to code it in the instruction .

If a processor can directly use the data in memory as operands , Then the processor must not be RISC The processor is .

5.7  abnormal

Except for branch type instructions , Many other situations can also interrupt the execution of the program , These conditions are collectively referred to as exceptions exception. Exceptions include ：

（1） Exception caused by an external event of the processor , It is more often called interruption interrupt, Because it happens outside the processor , Interrupts are not necessarily related to the instructions executed in the processor , The processor may be interrupted at any stage of execution , Therefore, it is also called asynchronous exception .

（2） The exception caused by the conversion from virtual address to physical address , For example, when this relationship does not exist with TLB in , It will produce TLB Missing exception , And if this conversion relationship does not exist in the page table , It will happen Page Fault A page table , Or a program accesses a protected page , Then an exception with wrong access rights will also be generated , Of course , If the processor does not implement virtual memory , Then these exceptions do not exist .

（3） The error caused by the instruction itself , For example, undefined instructions , Illegal instruction in user state , Overflow during integer operation , The address of the access memory is not aligned, etc . Many processors also support data integrity checking , For example, processor pair L2 Cache The sent data is parity checked or ECC check , If the check fails , Cause abnormal .

（4） Exception of the instruction itself , for example MIPS in SYSCALL and Trap.

From the outside of the processor , All instructions before the instructions that generate exceptions have been completed , The instruction that generates an exception and all subsequent instructions are not allowed to be completed . The processor will jump to the corresponding exception handler entry address , Start executing this exception handler , When its execution is completed , It will return to the place where the exception just happened , Let's start again. This instruction is taken into the pipeline , It's like this anomaly never happened , This method is also called precise anomaly precise exception.

  For most instructions with exceptions , All need to be executed again , But it's not absolute , Some types of exceptions cannot do this , A typical example is SYSCALL/Trap.

When an exception occurs , In order to return smoothly from the exception handler , You also need to when an exception occurs , Save the return address , This return address is the current exception instruction PC value .

about RISC For the processor , Generally, it is stored in a special register . for example MIPS Use in EPC Register to save the... When the exception occurs PC value ; And for CISC For the instruction set , Stack is usually used to save this PC value , The stack is actually a space in memory .

When an exception occurs , We also need to consider the processing of general registers , Because the contents of the general register may be changed in the exception handler , So when the exception handler starts , You need to save the involved registers , Whether it's CISC and RISC processor , Save the contents of the register to the stack . But for the RISC For the processor , To access memory , Only use load/store Instructions , So let's talk about the process of saving registers to the stack , Only use store Instructions , The pointer to the stack uses a general-purpose register to simulate .

And in the CISC In the processor , Set a special operation stack PUSH and POP Instructions , And use special registers as the stack , Use PUSH/POP Instructions , There is no need for software to manage stack pointers , The hardware will automatically increase or decrease it ,x86 The processor adopts this method . Actually in ARM Command set , It also uses PUSH/POP Instructions and special stack pointer registers .

In the processing of a pipeline , Exceptions may occur at all stages of the pipeline .

 （1） Take command stage fetch, Occurs when an instruction is fetched I-TLB Missing or even Page Fault, Or the address of the instruction does not exist , Or take instructions from the protected area ;

（2） decode decode： Undefined instruction encountered ;

（3） perform execute： Arithmetic operation overflow , Or in addition to 0 operation ;

（4） Access memory ： Occurs when accessing the data store D-TLB Missing or even Page Fault, Or the address to access the data memory does not exist , Or non aligned access .

The handling of exceptions should follow the original order in the program , In order to satisfy this condition , Sure   Make the processor handle exceptions uniformly at the last stage of the pipeline , Exceptions generated at other stages of the pipeline , All need to flow in the pipeline with instructions , It is not processed until the last stage of the pipeline , This ensures that exceptions are handled in the order specified in the program .

  Access memory in pipeline Memory After the phase , There will be no exception , Therefore, exceptions can be handled uniformly at this stage of memory access , Call this stage the exception handling point Commit Point. According to the definition of precise exception , The instruction with exception and all subsequent instructions cannot be completed , Therefore, when handling exceptions in the stage of accessing memory , You need to erase all instructions that enter the pipeline after this instruction , At the same time, the instruction that generates an exception cannot be completed , Therefore, this instruction is not allowed to enter the next writeback write back Stage .

In order to generate abnormal instructions PC It's worth saving , Each instruction pair will flow with the pipeline , So in the stage of accessing memory , This instruction can be corresponding to PC Value is saved to EPC Exception PC And village ,EPC The register is MIPS In the processor, it is specially used to save the abnormal instructions PC Value register , The type of exception will be recorded in another special register , This register is called Cause register , For exception handler query .