Usage of case, casez and casex statements in Verilog

List of articles

        1、case Usage of

        2、casez/casex Usage of

        3、case Statement

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1、case Usage of

        case Statement is a multiple choice structure statement , According to the expression （expression） The value in , For options （case_item） Match one by one from top to bottom . If there is an option corresponding to the expression , Execute the expression statement of this option （statement）, And from case Statement exit . If all options fail to match expression , execute default Statement in statement ; If there is no default Statement and none of the options match the expression , Then nothing is executed .

        case The general structure of the statement is as follows ：

        It should be noted that ：default Statement is optional （ Non mandatory ）, But in the general development process , To avoid creating latches LATCH, It is usually required to add default sentence . 

       

         Here is a use case A typical example of a statement ： 

        give an example ： The circuit will be based on the register rega Match the following options with the value of .

1. If rega = 16'd0, Execute the execution statement after the option is changed ----result = 10'b0111111111; And then quit case sentence .
2. If rega It's not equal to 16'd0, Then continue to search whether the next option matches , Until an option matches the expression , Then execute the execution statement of this option , sign out case sentence .
3. If rega The value of is not equal to any of these options , execute default The execution statement in the statement ----result = 'bx;

        although case The statement is matched from the first sentence to default sentence , But usually due to the heterogeneity of all options , So it created case Statements become de facto Parallel statements , There is no priority .

        

        Besides , We know Verilog HDL There are four basic values that represent level logic in hardware circuits ：

• 0： Logic 0 or " false "
• 1： Logic 1 or " really "
• x or X： Unknown
• z or Z： High resistance

        that case The statement of x/z How to support ？ The answer is , stay case In the sentence x Namely x, and z Namely z（ It sounds strange , It needs to be combined with the following casex/casez To understand the ）.

         Here is a list of options that have x、z Example ：

        Options 2'b0x、2'b0z、2'bx0 and 2'bz0 The corresponding execution statement will be executed only after an exact match . such as select[1:2] = 2'b0x And flaga = 0, be result = 0.

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2、casez/casex Usage of

        casez Statement and case The usage of the statement is very similar , The only difference is , state z stay casez Statements are not considered normal z state , Instead, the expression is , Marked as z the （ Or those ）bit As if you don't care （dont care）.

        Take the following example ：

          Options 8'b1??????? signify Back 7bit Don't care , Any value is OK , As long as the highest position is 1 That's it , So as to execute the following execution statements ----instruction1(ir);

        casex Statement and casez The usage of the statement is very similar , The only difference is ,casex The status can be changed at the same time x And status z Are deemed not to care （dont care）.

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3、case Statement

        case The value in an expression is a variable or a combination of variables , It can also be a constant .

         For example, the following way of writing ：

        Fix the value of the expression to a constant 1 be appointed after a period as acting , So just judge encode[2] Is it true , To be true is to carry out $display("Select Line 2") ; If false, judge  encode[1], until default.

        Write a simple testbench Check it out , By the way, when the expression options are not different from each other ,case Statement how to judge .

`timescale 1ns / 1ps			// Time unit / precision 

module tb_test();
 
reg [2:0] encode ;

initial begin
	encode = 3'b0;
	$display("sim start!");		// Simulation starts 
	#100
	#10 encode = 3'b100;
	#10 encode = 3'b010;
	#10 encode = 3'b001;
	
	#10 encode = 3'b111;		// At this point, all three options meet , Observe how 
	#10 encode = 3'b011;		// At this point, the last two options meet , Observe how 
	#20	$display("sim finish!");// End of simulation 
	$finish;
end

[email protected](*)begin
	case (1)
		encode[2] : $display("Select Line 2") ;
		encode[1] : $display("Select Line 1") ;
		encode[0] : $display("Select Line 0") ;
		default $display("Error: One of the bits expected ON");
	endcase
end 

endmodule

        Vivado The result of terminal window printing is as follows ：

1. Right now encode Initial value of assignment encode = 3'b0; Does not satisfy any of the options , perform default The execution statement in the statement , Show Error: One of the bits expected ON
2. Right now encode assignment     encode = 3'b100;  Satisfy encode[2], Execute the print statement Select Line 2
3. Right now encode assignment     encode = 3'b010; Satisfy encode[1], Execute the print statement Select Line 1
4. Right now encode assignment     encode = 3'b001; Satisfy encode[0], Execute the print statement Select Line 0
5. Right now encode assignment     encode = 3'b111;  Satisfy encode[2]、encode[1] and encode[0], But because of encode[2] At the top , So it will be matched to , Then execute the print statement Select Line 2（ explain case There are still priorities ）
6. Right now encode assignment     encode = 3'b011;  Satisfy encode[1] and encode[0], But because of encode[1] stay encode[0] above , So it will be matched to , Then execute the print statement Select Line 1（ Same description case There are priorities ）

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