VerilogA - dynamic comparator

 Dynamic clock controlled comparator , The rising edge triggers a comparison , Falling edge reset 

// VerilogA for SAR_SS_ADC,ideal_Comparator,veriloga //Auther:Li Yuandong

//Date:2022/5/12

`include"constants.vams" 
`include "disciplines.vams"

module ideal_Comparator(VINP,VINN,CLK,VOUTP,VOUTN); input VINP,VINN,CLK;

	output VOUTP,VOUTN;

	electrical VINP,VINN,CLK,VOUTP,VOUTN; 
	parameter real vtrans_clk=0.5;
	parameter real comp_slope=1000; 
	parameter real sigin_offset=0; 
	parameter real trise=0 from[0:inf); 
	parameter real tfall=0 from [0:inf); 
	parameter real tdel=0 from [0:inf); 
	integer m;
	integer n; 
	
	analog begin
		@(cross(V(CLK) -vtrans_clk, +1)) begin
			if( V(VINP) >= V(VINN))begin 
				m=1;
				n=0;
			end 
			else begin 
				m=0;
				n=1;
			end
		end

		@(cross(V(CLK) -vtrans_clk, -1)) begin 
			m=0;
			n=0;
		end

		V( VOUTP ) <+ transition( m?1:0,tdel,trise,tfall); 
		V( VOUTN ) <+ transition( n ? 1 : 0, tdel, trise, tfall ) ; 
	end

endmodule