[Verilog quick start of Niuke question series] ~ use functions to realize data size conversion

0. Preface

0.1 Knowledge point investigation

The investigation is ：

1. function function Knowledge points of ;
2. Understand big end and small end . Portal

0.2 Knowledge development

function and task The definition and difference of ？

This problem has been summarized before , Direct old rules , Poke an eye , Portal

1. VL10 Use function to realize data size conversion

1.1 Title Description

In digital chip design , Modules that implement specific functions are often written as function , Call again in the middle note module when needed. , In order to improve the reusability of code and improve the level of design , Subsequent modifications are made separately .

Please implement a function 4bit Function of data size conversion . Realize the conversion and output of two different inputs respectively .

1.1.1 Signal schematic diagram

1.1.2 Waveform diagram

This question is not officially given .

1.1.3 Input description

clk： The system clock
rst_n： Asynchronous reset signal , Low level active
a,b：4bit Unsigned number of bits wide

（ Pay attention to is ： The official code does not state clk and rst_n, Pay attention to add it by yourself when submitting ！！！）

1.1.4 Output description

c,d：4bit Unsigned number of bits wide

（ This should be an official clerical error , Four is right ）

1.2 Their thinking

The main thing is to investigate function Details of , The subject itself is not difficult , That is, the big end and the small end are converted . These knowledge points have been explained in the preface of this article , To view the .

1.3 Code implementation

`timescale 1ns/1ns
module function_mod(
    input clk,
    input rst_n,
	input [3:0]a,
	input [3:0]b,
	
	output [3:0]c,
	output [3:0]d
);
    function [3:0] big22small;
        input [3:0] big_small;
        begin
            big22small[0] = big_small[3];
            big22small[1] = big_small[2];
            big22small[2] = big_small[1];
            big22small[3] = big_small[0];
        end
    endfunction

    assign c = big22small(a);
    assign d = big22small(b);
endmodule

1.4 The test file

To be changed ...

1.5 Simulation waveform

To be changed ...