Development practice of ag1280q48 in domestic CPLD

================= introduction ===================================================

I bought a very simple one from a treasure yesterday AG1280Q48 Minimum system core board , Easy to run up a small lamp , I have agreed with some friends to provide the operation steps and detailed operation steps , Borrow this BLOG I realize from 0 Start writing simply .

AG1280Q48 It's a domestic CPLD, Internal 1280 individual LE, amount to EPM570 Twice the amount of logical resources , And in the traditional CPLD On this basis, a PLL And a built-in RAM, This is welfare . More importantly, the current price is only at 10 element RMB within , It can be said to be very sweet .

================== About FPGA/CPLD The two basic stages of development ===========================

FPGA The approximate workflow for developing software is as follows ：

step 1, First of all, we will VERILOG The code is analyzed and compiled into basic LUT Tables and registers , Although it's the same LUT surface , However, different functions can be realized by assigning different initial values to the interior . If other internal hard cores are used, such as PLL,DSP,RAM Instantiation is required . The result of this step is a net list （NETLIST）.

step 2,NETLIST It's like a schematic diagram PCB The library is imported to PCB In the document , The next step is layout and wiring , Put the original in the actual position , Generate for each FPGA/CPLD Internally connected switches and LUT Initialization file of . This step can be called routing , Or implementation “Implament”.

Of course, this is only the simplest step , Register copy ignored ,RETIMING, Timing constraints and other details .

The first step is actually formulaic , Just know one FPGA/CPLD The basic logical units used in it , It can be realized according to the mature accumulation algorithm verilog Code to base logical unit mapping . That's why SYNPLIFY The emergence of third-party integrated software . Especially in QUARTUS and ISE The age when comprehensive ability is not so strong , There is still a certain market for these third-party software . Its generation NETLIST To the corresponding manufacturer EDA Perform layout and routing, and finally realize the generation of configuration BIT flow .

We want to , If we design a CPLD/FPGA Hardware , The basic logic elements used internally are compatible with a certain model of an existing manufacturer , Then we can use the compilation tools of existing manufacturers to generate net lists in the first step above （NETLIST）, With this NETLIST Then we can use our own chip to LUT Information such as the placement and delay of the determines a specific LUT In which position , When necessary, in order to meet the time requirements, register copying is also required . These tasks require all kinds of information inside the chip of specific manufacturers , Only manufacturers can write this software .

===================AG1280Q48 The idea of software development ==============================

There are two basic steps mentioned above , In fact, the first step is more difficult , But foreign countries have mature algorithms and accumulated , After decades of development , It's mature . Domestic people are quite clever in making products , The first step is to borrow foreign development tools to generate NETLIST, Then you should do the second step to generate BIT flow , Finally, a download scheme will be implemented to generate BIT Stream burn into this CPLD Just go .

In addition, in pure RTL Make sure that there is no BRAM And other selected ALTERA Of FPGA/CPLD Built in hard core .

To be specific ：AQ1280Q48 The basic logical units used are compatible CYCLONE 4 Of , We do a simple pure without any hard core RTL Design , use VERILOG Write the code , Again QUARTUS Select any one of them CYLONE 4 The model of , Make sure there are no errors in the code . stay AG Specified under software QUARTUS Project directory , after AG The software automatically converts from one directory to another QUARTUS project , Put this QURTUS Compile the project and generate it again NETLIST. After that, enter AG The software performs the layout and wiring .

The above steps are pure RTL Compilation of , and AG1280Q48 There are also two hard cores. One is PLL One is BRAM, Because these two are not pure RTL It can't be converted into LUT, Therefore, the following operations should be performed accordingly ：

1, take PLL perhaps BRAM Set to DESIGN PARTITION.

2, Add simulation file , Substitute the description inside for the real one PLL and BRAM modular

The basic steps are as follows BLOG Just practice this process in detail .

With the above principle analysis, the following practical operation steps are easy to understand and operate

Here are some links you can refer to ：

https://github.com/xjtuecho/agmpill

AG1280Q48 Minimum system board V1 - Jialichuang EDA Open source hardware platform

Share a home-made CPLD/FPGA Chip data ：AGM Of AG1280Q48 / Xilinx/Altera/FPGA/CPLD/Verilog / WhyCan Forum( Wow, cool developer community )

domestic AGM FPGA A detailed introduction to the design process - Electronic enthusiast network